好书推荐Trade-Offs In Analog Circuit Design

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Trade-Offs in Analog Circuit Design

The Designer’s Companion
Edited by Chris Toumazou
Imperial College, UK
George Moschytz
ETH-Zentrum, Switzerland
and Barrie Gilbert
Analog Devices, USA
Editing Assistance
Ganesh Kathiresan
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47673-8
Print ISBN: 1-4020-7037-3
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2002 Kluwer Academic Publishers
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
and Kluwer's eBookstore at: http://ebooks.kluweronline.com
Dordrecht

Contents
Foreword
List of Contributors
xxiii
xxix
Design Methodology
Intuitive Analog Circuit Design
Chris Toumazou
Mass-Production of Microdevices
2.1.1 Present Objectives
Unique Challenges of Analog Design
2.2.1 Analog is Newtonian
Designing with Manufacture in Mind
2.3.1 Conflicts and Compromises
2.3.2 Coping with Sensitivities: DAPs, TAPs and STMs
Robustness, Optimization and Trade-Offs
2.4.1 Choice of Architecture
2.4.2 Choice of Technology and Topology
2.4.3 Remedies for Non-Robust Practices
2.4.4 Turning the Tables on a Non-Robust Circuit: A Case Study
Holistic optimization of the LNA
A further example of biasing synergy
2.4.5 Robustness in Voltage References
2.4.6 The Cost of Robustness
Toward Design Mastery
2.5.1 First, the Finale
2.5.2 Consider All Deliverables
2.5.3 Design Compression
2.5.4 Fundamentals before Finesse
2.5.5 Re-Utilization of Proven Cells
2.5.6 Try to Break Your Circuits
2.5.7 Use Corner Modeling Judiciously
2.5.8 Use Large-Signal Time-Domain Methods
2.5.9 Use Back-Annotation of Parasitics
2.5.10 Make Your Intentions Clear
2.5.11 Dubious Value of Check Lists
2.5.12 Use the “Ten Things That Will Fail” Test
Conclusion
1
1
2
6
7
7
9
Design for Manufacture
Barrie Gilbert
1
1.1
1.2
Introduction
The Analog Dilemma
References
2
2.1
2.2
2.3
2.4
2.5
2.6
11
13
14
15
16
22
25
27
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v
vi Contents
General Performance
3
Trade-Offs in CMOS VLSI Circuits
Andrey V. Mezhiba and Eby G. Friedman
75
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Area
Speed
Power
Design Productivity
Testability
Reliability
Noise Tolerance
Packaging
General Considerations
Power dissipation in CMOS VLSI circuits
Technology scaling
VLSI design methodologies
Structural Level
3.3.1 Parallel Architecture
3.3.2 Pipelining
Circuit Level
3.4.1 Static versus Dynamic
3.4.2 Transistor Sizing
3.4.3 Tapered Buffers
Physical Level
Process Level
3.6.1 Scaling
3.6.2 Threshold Voltage
3.6.3 Power Supply
3.6.4 Improved Interconnect and Dielectric Materials
Future Trends
75
78
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108
115
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118
118
119
Glossary
References
4
Floating-gate Circuits and Systems
Tor Sverre Lande
4.1
4.2
4.3
UV-conductance
Fowler–Nordheim Tunneling
Hot Carrier Injection
Introduction
Design Criteria
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
Introduction
Device Physics
4.2.1
4.2.2
4.2.3
Programming
4.3.1
4.3.2
4.3.3
Contents vii
4.4
4.5
4.6
4.7
Circuit Elements
4.4.1 Programming Circuits
Inter-poly tunneling
Example: Floating-gate on-chip knobs
Inter-poly UV-programming
MOS-transistor UV-conductance
Example: MOS transistor threshold tuning
Combined programming techniques
Example: Single transistor synapse
High-voltage drivers
FGMOS Circuits and Systems
4.5.1 Autozero Floating-Gate Amplifier
4.5.2 Low-power/Low-voltage Rail-to-Rail Circuits Using FGUVMOS
Digital FGUVMOS circuits
Low-voltage rail-to-rail FGUVMOS amplifier
4.5.3 Adaptive Retina
4.5.4 Other Circuits
Retention
Concluding Remarks
References
5
119
120
120
121
121
122
123
124
126
127
128
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141
142
143
144
146
147
148
150
151
152
153
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155
156
157
157
159
163
164
Bandgap Reference Design
Arie van Staveren, Michiel H. L. Kouwenhoven, Wouter A. Serdijn and Chris
J. M. Verhoeven
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Introduction
The Basic Function
Temperature Behavior of
General Temperature Compensation
A Linear Combination of Base–Emitter Voltages
5.5.1 First-Order Compensation
5.5.2 Second-Order Compensation
The Key Parameters
Temperature-Dependent Resistors
Noise
5.8.1 Noise of the Idealized Bandgap Reference
5.8.2 Noise of a First-Order Compensated Reference
5.8.3 Noise of a Second-Order Compensated Reference
5.8.4 Power-Supply Rejection
Simplified Structures
5.9.1 First-Order Compensated Reference
5.9.2 Second-Order Compensated Reference
Design Example
5.10.1 First-Order Compensated Bandgap Reference
5.10.2 Second-Order Compensated Bandgap Reference
Conclusions
References
viii Contents
6
Generalized Feedback Circuit Analysis
Scott K. Burgess and John Choma, Jr.
6.1
6.2
6.3
Introduction
Fundamental Properties of Feedback Loops
6.2.1 Open Loop System Architecture and Parameters
6.2.2 Closed Loop System Parameters
6.2.3 Phase Margin
6.2.4 Settling Time
Circuit Partitioning
6.3.1 Generalized Circuit Transfer Function
6.3.2 Generalized Driving Point I/O Impedances
6.3.3 Special Controlling/Controlled Port Cases
Controlling feedback variable is the circuit output variable
Global feedback
Controlling feedback variable is the branch variable of the controlled port
References
169
169
171
171
173
176
179
182
183
189
191
192
193
195
204
7
Analog Amplifiers Architectures: Gain Bandwidth Trade-Offs
Alison J. Burdett and Chris Toumazou
7.1
7.2
7.3
7.4
7.5
7.6
Introduction
Early Concepts in Amplifier Theory
7.2.1 The Ideal Amplifier
7.2.2 Reciprocity and Adjoint Networks
7.2.3 The Ideal Amplifier Set
Practical Amplifier Implementations
7.3.1 Voltage Op-Amps
7.3.2 Breaking the Gain–Bandwidth Conflict
Current-feedback op-amps
Follower-based amplifiers
Current-conveyor amplifiers
7.3.3 Producing a Controlled Output Current
Closed-Loop Amplifier Performance
7.4.1 Ideal Amplifiers
7.4.2 Real Amplifiers
Source and Load Isolation
Conclusions
References
207
207
208
208
209
210
211
211
213
213
214
214
215
217
217
218
222
224
225
8
Noise, Gain and Bandwidth in Analog Design
Robert G. Meyer
8.1
8.2
8.3
Gain–Bandwidth Concepts
8.1.1 Gain–Bandwidth Shrinkage
8.1.2 Gain–Bandwidth Trade-Offs Using Inductors
Device Noise Representation
8.2.1 Effect of Inductors on Noise Performance
Trade-Offs in Noise and Gain–Bandwidth
227
227
230
232
234
238
240
Contents ix
8.3.1
8.3.2
8.3.3
Methods of Trading Gain for Bandwidth and the Associated Noise
Performance Implications [8]
The Use of Single-Stage Feedback for the Noise-Gain–Bandwidth
Trade-Off
Use of Multi-Stage Feedback to Trade-Off Gain, Bandwidth and
Noise Performance
240
243
248
255
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283
283
284
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306
References
9
Frequency Compensation
Arie van Staveren, Michiel H. L. Kouwenhoven, Wouter A. Serdijn and Chris J. M.
Verhoeven
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Introduction
Design Objective
The Asymptotic-Gain Model
The Maximum Attainable Bandwidth
9.4.1 The LP Product
9.4.2 The Group of Dominant Poles
Pole Placement
9.5.1 Resistive Broadbanding
9.5.2 Pole–Zero Cancelation
9.5.3 Pole Splitting
9.5.4 Phantom Zeros
9.5.5 Order of Preference
Adding Second-Order Effects
Example Design
Conclusion
References
10
Frequency-Dynamic Range-Power
Eric A. Vittoz and Yannis P. Tsividis
10.1
10.2
10.3
10.4
Introduction
Fundamental Limits of Trade-Off
10.2.1 Absolute Lower Boundary
10.2.2 Filters
10.2.3 Oscillators
10.2.4 Voltage-to-Current and Current-to-Voltage Conversion
10.2.5 Current Amplifiers
10.2.6 Voltage Amplifiers
Process-Dependent Limitations
10.3.1 Parasitic Capacitors
10.3.2 Additional Sources of Noise
10.3.3 Mismatch of Components
10.3.4 Charge Injection
10.3.5 Non-Optimum Supply Voltage
Companding and Dynamic Biasing
10.4.1 Syllabic Companding
10.4.2 Dynamic Biasing
x Contents
10.4.3 Performance in the Presence of blockers
10.4.4 Instantaneous Companding
Conclusion 10.5
308
309
310
311 References
Filters
11
Trade-Offs in Sensitivity, Component Spread and Component Tolerance in
Active Filter Design
George Moschytz
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Introduction
Basics of Sensitivity Theory
The Component Sensitivity of Active Filters
Filter Selectivity, Pole Q and Sensitivity
Maximizing the Selectivity of RC Networks
Some Design Examples
Sensitivity and Noise
Summary and Conclusions
References
315
315
316
319
325
328
332
337
339
339
341
341
341
342
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353
12
Continuous-Time Filters
Robert Fox
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
Introduction
Filter-Design Trade-Offs: Selectivity, Filter Order, Pole Q and
Transient Response
Circuit Trade-Offs
12.3.1 Linearity vs Tuneability
12.3.2 Passive Components
12.3.3 Tuneable Resistance Using MOSFETs: The MOSFET-C Approach
The Transconductance-C (Gm-C) Approach
12.4.1 Triode-Region Transconductors
12.4.2 Saturation-Region Transconductors
12.4.3 MOSFETs Used for Degeneration
12.4.4 BJT-Based Transconductors
12.4.5 Offset Differential Pairs
Dynamic Range
Differential Operation
Log-Domain Filtering
Transconductor Frequency-Response Trade-Offs
Tuning Trade-Offs
No tuning
Off-chip tuning
One-time post-fabrication tuning
Automatic tuning
Simulation Issues
References
Contents xi
13
Insights in Log-Domain Filtering
Emmanuel M. Drakakis and Alison J. Burdett
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
General
Synthesis and Design of Log-Domain Filters
Impact of BJT Non-Idealities upon Log-Domain Transfer Functions:
The Lowpass Biquad Example
Floating Capacitor-Based Realization of Finite Transmission Zeros in
Log-Domain: The Impact upon Linearity
Effect of Modulation Index upon Internal Log-Domain Current Bandwidth
Distortion Properties of Log-Domain Circuits: The Lossy Integrator Case
Noise Properties of Log-Domain Circuits: The Lossy Integrator Case
Summary
References
Switched Circuits
14
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374
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383
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393
401
401
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408
409
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421
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446
447
447
448
Trade-offs in the Design of CMOS Comparators
A. Rodríguez-Vázquez, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and
J.M. de la Rosa
14.1
14.2
14.3
14.4
14.5
14.6
Introduction
Overview of Basic CMOS Voltage Comparator Architectures
14.2.1 Single-Step Voltage Comparators
14.2.2 Multistep Comparators
14.2.3 Regenerative Positive-Feedback Comparators
14.2.4 Pre-Amplified Regenerative Comparators
Architectural Speed vs Resolution Trade-Offs
14.3.1 Single-Step Comparators
14.3.2 Multistep Comparators
14.3.3 Regenerative Comparators
On the impact of the offset
Offset-Compensated Comparators
14.5.1 Offset-Compensation Through Dynamic Biasing
14.5.2 Offset Compensation in Multistep Comparators
14.5.3 Residual Offset and Gain Degradation in Self-Biased Comparators
14.5.4 Transient Behavior and Dynamic Resolution in Self-Biased
Comparators
Appendix. Simplified MOST Model
References
15
Switched-Capacitor Circuits
Andrea Baschirotto
15.1
15.2
Introduction
Trade-Off due to Scaled CMOS Technology
15.2.1 Reduction of the MOS Output Impedance
15.2.2 Increase of the Flicker Noise
15.2.3 Increase of the MOS Leakage Current
15.2.4 Reduction of the Supply Voltage
xii Contents
15.3
15.4
Trade-Off in High-Frequency SC Circuits
15.3.1 Trade-Off Between an IIR and a FIR Frequency Response
15.3.2 Trade-Off in SC Parallel Solutions
15.3.3 Trade-Off in the Frequency Choice
Conclusions
Acknowledgments
References
451
452
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498
16
Compatibility of SC Technique with Digital VLSI Technology
Kritsapon Leelavattananon and Chris Toumazou
16.1
16.2
16.3
16.4
16.5
16.6
16.7
Introduction
Monolithic MOS Capacitors Available in Digital VLSI Processes
16.2.1 Polysilicon-over-Polysilicon (or Double-Poly) Structure
16.2.2 Polysilicon-over-Diffusion Structure
16.2.3 Metal-over-Metal Structure
16.2.4 Metal-over-Polysilicon Structure
16.2.5 MOSFET Gate Structure
Operational Amplifiers in Standard VLSI Processes
16.3.1 Operational Amplifier Topologies
Single-stage (telescopic) amplifier
Folded cascode amplifier
Gain-boosting amplifier
Two-stage amplifier
16.3.2 Frequency Compensation
Miller compensation
Miller compensation incorporating source follower
Cascode Miller Compensation
16.3.3 Common-Mode Feedback
Charge-Domain Processing
Linearity Enhanced Composite Capacitor Branches
16.5.1 Series Compensation Capacitor Branch
16.5.2 Parallel Compensation Capacitor Branch
16.5.3 Balanced Compensation Capacitor Branch
Practical Considerations
16.6.1 Bias Voltage Mismatch
16.6.2 Capacitor Mismatch
16.6.3 Parasitic Capacitances
Summary
References
17
Switched-Capacitors or Switched-Currents – Which Will Succeed?
John Hughes and Apisak Worapishet
17.1
17.2
17.3
Introduction
Test Vehicles and Performance Criteria
Clock Frequency
17.3.1
17.3.2
17.3.3
Switched-Capacitor Settling
Switched-Currents Class A Settling
Switched-Currents Class AB Settling
Contents xiii
17.4
17.5
17.6
17.7
17.8
Power Consumption
17.4.1 Switched-Capacitors and Switched-Currents Class A Power
Consumption
17.4.2 Switched-Currents Class AB Power Consumption
Signal-to-Noise Ratio
17.5.1 Switched-Capacitors Noise
17.5.2 Switched-Currents Class A Noise
17.5.3 Switched-Current Class AB Noise
17.5.4 Comparison of Signal-to-Noise Ratios
Figure-of-Merit
17.6.1 Switched-Capacitors
17.6.2 Switched-Currents Class A
17.6.3 Switched-Currents Class AB
Comparison of Figures-of-Merit
Conclusions
499
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506
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509
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556
References
Oscillators
18
Design of Integrated LC VCOS
Donhee Ham
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
Introduction
Graphical Nonlinear Programming
LC VCO Design Constraints and an Objective Function
18.3.1 Design Constraints
18.3.2 Phase Noise as an Objective Function
18.3.3 Phase Noise Approximation
18.3.4 Independent Design Variables
LC VCO Optimization via GNP
18.4.1 Example of Design Constraints
18.4.2 GNP with a Fixed Inductor
18.4.3 GNP with a Fixed Inductance Value
18.4.4 Inductance and Current Selection
18.4.5 Summary of the Optimization Process
18.4.6 Remarks on Final Adjustment and Robust Design
Discussion on LC VCO Optimization
Simulation
Experimental Results
Conclusion
Acknowledgments
References
19
Trade-Offs in Oscillator Phase Noise
Ali Hajimiri
19.1
19.2
Motivation
Measures of Frequency Instability
19.2.1 Phase Noise
19.2.2 Timing Jitter
xiv Contents
19.3
19.4
19.5
Phase Noise Modeling
19.3.1 Up-Conversion of 1 / f Noise
19.3.2 Time-Varying Noise Sources
Phase Noise Trade-Offs in LC Oscillators
19.4.1 Tank Voltage Amplitude
19.4.2 Noise Sources
Stationary noise approximation
Cyclostationary noise sources
19.4.3 Design Implications
Phase Noise Trade-Offs for Ring Oscillators
19.5.1 The Impulse Sensitivity Function for Ring Oscillators
19.5.2 Expressions for Phase Noise in Ring Oscillators
19.5.3 Substrate and Supply Noise
19.5.4 Design Trade-Offs in Ring Oscillators
References
557
562
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565
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570
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603
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604
604
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610
610
610
Data Converters
20
Systematic Design of High-Performance Data Converters
Georges Gielen, Jan Vandenbussche, Geert Van der Plas, Walter Daems, Anne Van den
Bosch, Michiel Steyaert and Willy Sansen
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
Introduction
Systematic Design Flow for D/A Converters
Current-Steering D/A Converter Architecture
Generic Behavioral Modeling for the Top-Down Phase
Sizing Synthesis of the D/A Converter
20.5.1 Architectural-Level Synthesis
Static performance
Dynamic performance
20.5.2 Circuit-Level Synthesis
Static performance
Dynamic performance
20.5.3 Full Decoder Synthesis
20.5.4 Clock Driver Synthesis
Layout Synthesis of the D/A Converter
20.6.1 Floorplanning
20.6.2 Circuit and Module Layout Generation
Current-source array layout generation
Swatch array layout generation
Full decoder standard cell place and route
20.6.3 Converter Layout Assembly
Extracted Behavioral Model for Bottom-Up Verification
Experimental Results
Conclusions
Acknowledgments
References
Contents xv
21
Analog Power Modeling for Data Converters and Filters
Georges Gielen and Erik Lauwers
613
613
614
616
616
619
620
620
621
624
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625
626
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21.1
21.2
21.3
21.4
21.5
Introduction
Approaches for Analog Power Estimators
A Power Estimation Model for High-Speed Nyquist-Rate ADCs
21.3.1 The Power Estimator Derivation
21.3.2 Results of the Power Estimator
A Power Estimation Model for Analog Continuous-Time Filters
21.4.1 The ACTIF Approach
21.4.2 Description of the Filter Synthesis Part
21.4.3 OTA Behavioral Modeling and Optimization for Minimal Power
Consumption
Modeling of the transconductances
The distortion model
Optimization
21.4.4 Experimental Results
Conclusions
Acknowledgment
References
22
Speed vs. dynamic range Trade-Off in Oversampling Data Converters
Richard Schreier, Jesper Steensgaard and Gabor C. Temes
22.1
22.2
22.3
22.4
Introduction
Oversampling Data Converters
22.2.1 Quantization Error
22.2.2 Feedback Quantizers
22.2.3 Oversampling D/A Converters
22.2.4 Oversampling A/D Converters
22.2.5 Multibit Quantization
Mismatch Shaping
22.3.1 Element Rotation
22.3.2 Generalized Mismatch-Shaping
22.3.3 Other Mismatch-Shaping Architectures
22.3.4 Performance Comparison
Reconstructing a Sampled Signal
22.4.1 The Interpolation Process
An interpolation system example
22.4.2 Fundamental Architectures for Practical Implementations
Single-bit delta–sigma modulation
Multibit delta–sigma modulation
High-resolution oversampled D/A converters
22.4.3 High-Resolution Mismatch-Shaping D/A Converters
A fresh look on mismatch shaping
Practical implementations
References
xvi Contents
Transceivers
23
Power-Conscious Design of Wireless Circuits and Systems
Asad A. Abidi
23.1
23.2
23.3
665
665
667
668
668
670
671
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678
681
685
686
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697
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707
709
712
714
718
718
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723
725
725
726
728
732
732
734
735
Introduction
Lowering Power across the Hierarchy
Power Conscious RF and Baseband Circuits
23.3.1 Dynamic Range and Power Consumption
23.3.2 Lowering Power in Tuned Circuits
23.3.3 Importance of Passives Quality in Resonant Circuits
23.3.4 Low Noise Amplifiers
23.3.5 Oscillators
23.3.6 Mixers
23.3.7 Frequency Dividers
23.3.8 Baseband Circuits
23.3.9 On-Chip Inductors
23.3.10 Examples of Low Power Radio Implementations
23.3.11 Conclusions: Circuits
References
24
Photoreceiver Design
Mark Forbes
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
Introduction
Review of Receiver Structure
Front-End Small-Signal Performance
24.3.1 Small-Signal Analysis
24.3.2 Speed/Sensitivity Trade-Off
24.3.3 Calculations, for example, parameters
Noise Limits
Post-Amplifier Performance
Front-End and Post-Amplifier Combined Trade-Off
Mismatch
Conclusions
Acknowledgments
References
25
Analog Front-End Design Considerations for DSL
Nianxiong Nick Tan
25.1
25.2
25.3
Introduction
System Considerations
25.2.1 Digital vs Analog Process
25.2.2 Active vs Passive Filters
Data Converter Requirements for DSL
25.3.1 Optimum Data Converters for ADSL
Optimum ADCs for ADSL
Optimum ADC for ADSL-CO
Optimum ADC for ADSL-CP
Contents xvii
25.4
25.5
Optimum DACs
Optimum DAC for ADSL-CO
Optimum DAC for ADSL-CP
25.3.2 Function of Filtering
Circuit Considerations
25.4.1 Oversampling vs Nyquist Data Converters
25.4.2 SI vs SC
25.4.3 Sampled-Data vs Continuous-Time Filters
25.4.4 Gm-C vs RC filters
Conclusions
Acknowledgments
References
735
737
737
738
740
740
743
743
744
744
745
745
747
747
747
748
749
749
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750
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759
760
761
762
762
763
764
765
765
766
766
767
769
770
772
773
773
26
Low Noise Design
Michiel H. L. Kouwenhoven, Arie van Staveren, WouterA. Serdijn and
Chris J. M. Verhoeven
26.1
26.2
26.3
26.4
26.5
Introduction
Noise Analysis Tools
26.2.1 Equivalent Noise Source
26.2.2 Transform-I: Voltage Source Shift
26.2.3 Transform-II: Current Source Shift
26.2.4 Transform-III: Norton-Thévenin Transform
26.2.5 Transform-IV: Shift through Twoports
Low-Noise Amplifier Design
26.3.1 Design of the Feedback Network
Noise production by the feedback network
Magnification of nullor noise
Distortion increment and bandwidth reduction
26.3.2 Design of the Active Part for Low Noise
26.3.3 Noise Optimizations
Noise matching to the source
Optimization of the bias current
Connecting stages in series/parallel
Summary of optimizations
Low Noise Harmonic Resonator Oscillator Design
26.4.1 General Structure of a Resonator Oscillator
26.4.2 Noise Contribution of the Resonator
26.4.3 Design of the Undamping Circuit for Low Noise
Principle implementation of the undamping circuit
Amplitude control
Noise performance
Driving the oscillator load
26.4.4 Noise Matching of the Resonator and Undamping Circuit: Tapping
26.4.5 Power Matching
26.4.6 Coupled Resonator Oscillators
Low-Noise Relaxation Oscillator Design
26.5.1 Phase Noise in Relaxation Oscillators
Simple phase noise model
xviii Contents
Influence of the memory on the oscillator phase noise
Influence of comparators on the oscillator phase noise
26.5.2 Improvement of the Noise Behavior by Alternative Topologies
Relaxation oscillators with memory bypass
Coupled relaxation oscillators
References
774
776
777
778
780
784
787
787
788
789
789
791
792
793
794
796
797
799
799
800
800
803
805
805
805
806
807
809
809
811
812
813
814
814
815
817
817
821
821
822
822
823
27
Trade-Offs in CMOS Mixer Design
Ganesh Kathiresan and Chris Toumazou
27.1
27.2
27.3
27.4
27.5
Introduction
27.1.1 The RF Receiver Re-Visited
Some Mixer Basics
27.2.1 Mixers vs Multipliers
27.2.2 Mixers: Nonlinear or Linear-Time-Variant?
Mixer Figures of Merit
27.3.1 Conversion Gain and Bandwidth
27.3.2 1 dB Compression Point
27.3.3 Third-Order Intercept Point
27.3.4 Noise Figure
27.3.5 Port-to-Port Isolation
27.3.6 Common Mode Rejection, Power Supply, etc
Mixer Architectures and Trade-Offs
27.4.1 Single Balanced Differential Pair Mixer
27.4.2 Double-Balanced Mixer and Its Conversion Gain
27.4.3 Supply Voltage
Active loads
Inductive current source
Two stack source coupled mixer
Bulk driven topologies
27.4.4 Linearity
Source degeneration
Switched MOSFET degeneration
27.4.5 LO Feedthrough
27.4.6 Mixer Noise
Noise due to the load
Noise due to the input transconductor
Noise due to the switches
Conclusion
References
28
A High-performance Dynamic-logic Phase-Frequency Detector
Shenggao Li and Mohammed Ismail
28.1
28.2
Introduction
Phase Detectors Review
28.2.1 Multiplier
28.2.2 Exclusive-OR Gate
Contents xix
28.3
28.4
28.5
28.6
28.2.3 JK-Flipflop
28.2.4 Tri-State Phase Detector
Design Issues in Phase-Frequency Detectors
28.3.1 Dead-Zone
28.3.2 Blind-Zone
Dynamic Logic Phase-Frequency Detectors
A Novel Dynamic-Logic Phase-Frequency Detector
28.5.1 Circuit Operation
28.5.2 Performance Evaluation
Conclusion
825
825
827
827
829
831
835
836
837
842
842
843
843
845
845
848
848
849
850
852
853
853
857
858
861
863
863
865
869
869
870
872
872
878
880
883
883
884
886
887
887
References
29
Trade-Offs in Power Amplifiers
Chung Kei Thomas Chan, Steve Hung-Lung Tu and Chris Toumazou
29.1
29.2
29.3
29.4
29.5
Introduction
Classification of Power Amplifiers
29.2.1 Current-Source Power Amplifiers
29.2.2 Switch-Mode Power Amplifiers
Class D power amplifier
Class E power amplifier
Class F power amplifier
29.2.3 Bandwidth Efficiency, Power Efficiency and Linearity
Effect of Loaded Q-Factor on Class E Power Amplifiers
29.3.1 Circuit Analysis
29.3.2 Power Efficiency
29.3.3 Circuit Simulation and Discussion
Class E Power Amplifiers with Nonlinear Shunt Capacitance
29.4.1 Numerical Computation of Optimum Component Values
Basic equations
Optimum operation (Alinikula’s method [16])
Fourier analysis
Normalized power capability
29.4.2 Generalized Numerical Method
Design example
Small linear shunt capacitor
Conclusion
References
Neural Processing
30
Trade-Offs in Standard and Universal CNN Cells
Martin Hänggi, Radu Dogaru and Leon O. Chua
30.1
30.2
30.3
Introduction
The Standard CNN
30.2.1 Circuit Implementation of CNNs
Standard CNN Cells: Robustness vs Processing Speed
30.3.1 Reliability of a Standard CNN
xx Contents
Introduction
Absolute and relative robustness
The Robustness of a CNN template set
Template scaling
Template design
30.3.2 The Settling Time of a Standard CNN
Introduction
The exact approach for uncoupled CNNS
30.3.3 Analysis of Propagation-Type Templates
Introduction
Examples of propagation-type templates
30.3.4 Robust CNN Algorithms for High-Connectivity Tasks
Template classes
One-step vs algorithmic processing
30.3.5 Concluding Remarks
Universal CNN Cells and their Trade-Offs
30.4.1 Preliminaries
30.4.2 Pyramidal CNN cells
Architecture
Trade-offs
30.4.3 Canonical Piecewise-linear CNN cells
Characterization and architecture
Trade-offs
Example
30.4.4 The Multi-Nested Universal CNN Cell
Architecture and characterization
Trade-offs
30.4.5 An RTD-Based Multi-Nested Universal CNN Cell Circuit
30.4.6 Concluding Remarks
References
887
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890
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893
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902
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907
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909
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925
926
927
928
929
929
930
931
932
938
941
943
945
30.4
Analog CAD
31
Top–Down Design Methodology For Analog Circuits Using Matlab and Simulink
Naveen Chandra and Gordon W. Roberts
31.1
31.2
31.3
31.4
31.5
Introduction
Design Methodology Motivation
31.2.1 Optimization Procedure
Switched Capacitor Delta–Sigma Design Procedure
31.3.1 Switched Sampled Capacitor (kT/C) Noise
31.3.2 OTA Parameters
Modeling of Modulators in Simulink
31.4.1 Sampled Capacitor (kT/C) Noise
31.4.2 OTA Noise
31.4.3 Switched Capacitor Integrator Non-Idealities
Optimization Setup
31.5.1 Implementation in Matlab
31.5.2 Initial Conditions
31.5.3 Additional Factors
Contents xxi
31.6
31.7
31.8
Summary of Simulation Results
A Fully Coded Modulator Design Example
Conclusion
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985
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988
989
992
993
996
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1000
1006
1009
1010
References
32
Techniques and Applications of Symbolic Analysis for Analog Integrated Circuits
Georges Gielen
32.1
32.2
32.3
32.4
32.5
32.6
Introduction
What is Symbolic Analysis?
32.2.1 Definition of Symbolic Analysis
32.2.2 Basic Methodology of Symbolic Analysis
Applications of Symbolic Analysis
32.3.1 Insight into Circuit Behavior
32.3.2 Analytic Model Generation for Automated Analog Circuit Sizing
32.3.3 Interactive Circuit Exploration
32.3.4 Repetitive Formula Evaluation
32.3.5 Analog Fault Diagnosis
32.3.6 Behavioral Model Generation
32.3.7 Formal Verification
32.3.8 Summary of Applications
Present Capabilities and Limitations of Symbolic Analysis
32.4.1 Symbolic Approximation
32.4.2 Improving Computational Efficiency
32.4.3 Simplification During Generation
32.4.4 Simplification Before Generation
32.4.5 Hierarchical Decomposition
32.4.6 Symbolic Pole–Zero Analysis
32.4.7 Symbolic Distortion Analysis
32.4.8 Open Research Topics
Comparison of Symbolic Simulators
Conclusions
Acknowledgments
References
33
Topics in IC Layout for Manufacture
Barrie Gilbert
33.1
33.2
33.3
33.4
Layout: The Crucial Next Step
33.1.1 An Architectural Analogy
33.1.2 IC Layout: A Matter of “Drafting”?
33.1.3 A Shared Undertaking
33.1.4 What Inputs should the Layouteer Expect?
Interconnects
33.2.1 Metal Limitations
33.2.2 Other Metalization Trade-Offs
Substrates and the Myth of “Ground”
33.3.1 Device-Level Substrate Nodes
Starting an Analog Layout
xxii Contents
33.5
33.6
33.7
Device Matching
33.5.1 The “Biggest-of-All” Layout Trade-Off
33.5.2 Matching Rules for Specific Components
33.5.3 Capacitor Matching
33.5.4 Circuit/Layout Synergy
Layout of Silicon-on-Insulator Processes
33.6.1 Consequences of High Thermal Resistance
Reflections on Superintegrated Layout
1012
1015
1016
1018
1020
1024
1028
1029
1033 Index

mk2708123

下面给出该书的分卷压缩pdf文档
Trade-Offs In Analog Circuit Design [rds].part1

mk2708123

Trade-Offs In Analog Circuit Design [rds].part2

mk2708123

Trade-Offs In Analog Circuit Design [rds].part3

mk2708123

Trade-Offs In Analog Circuit Design [rds].part4

mk2708123

Trade-Offs In Analog Circuit Design [rds].part5

mk2708123

Trade-Offs In Analog Circuit Design [rds].part6

mk2708123

Trade-Offs In Analog Circuit Design [rds].part7

总共7卷，只有全部下载下来以后，才能解压缩，而且必须按照part1,part2.....的顺序下载，不然即使全部下载下来以后，也无法正常解压缩，我以前下载的时候，有一次，没有按照顺序从part1下载，结果最后还是没法解压缩，当时可真是郁闷，希望大家不要犯和我一样的错误，以免白白浪费积分

顺便说一下，我提供的是英文原版的电子文档，不是扫描版，插图和字体都很清楚，全书共1048页，内容很全面，可以当一个不错的参考资料来收藏

mk2708123

Trade-Offs In Analog Circuit Design [rds].part7

mk2708123

不好意思，操作失误，part7多上传了一次