小弟初学verilog， 有个问题哪位大侠给解答一下

8i8i9o9o

请看下面verilog code1.
为什么会这样写？

if (mclk)

data_tmp <= #1 -1;


赋值data_tmp是一个负数？

2.
// perform timing checks

这行以下的删掉也可以是吗，不参与综合吧？

谢谢

module ram (data, a, mclk, rdb, wrb);

parameter MSB = 27;
parameter ADDR = 5;
parameter SIZE = 32;

    inout [MSB:0] data;
    input [ADDR-1:0] a;
    input mclk;
    input rdb;
    input wrb;



reg [MSB:0] ramcore[SIZE:0];
reg [MSB:0] data_tmp;
wire [MSB:0] data = rdb ? 'bz : data_tmp;

always @(mclk or a or wrb or rdb)

if (mclk)

data_tmp <= #1 -1;

else if(~wrb)

ramcore[a]=data;

else if (~rdb)

data_tmp <= #1 ramcore[a];

else

data_tmp <= #1 -1;

always @(a or wrb or rdb)

if(~mclk) $display("ERROR!!! RAM address or RDb/WRb changing while mclk=0 at time=%d",$time);

integer cnt;
initial begin

cnt=0;

while(cnt<32) begin

ramcore[cnt]=0;

cnt=cnt+1;

end
end


//**********************************************
// perform timing checks
//**********************************************

   reg clk_valid;
   reg error_toggle;

   initial
   begin
      clk_valid = 0;
      error_toggle = 0;
   end

   wire #(1) del_clk = mclk;

   always @(negedge mclk && !clk_valid)
      if ((~mclk & del_clk) === 1'b1) clk_valid = 1;

   wire valid_sig = clk_valid;


   specify
      specparam t_clk_high   = 1:1:1;  // Min clock high time
      specparam t_clk_low    = 1:1:1;  // Min clock low time

      specparam t_data_setup = 1:1:1;  // Write data setup time
      specparam t_data_hold  = 0:0:0;  // Write data hold time

      specparam t_addr_setup = 1:1:1;  // Address setup time
      specparam t_addr_hold  = 0:0:0;  // Address hold time

      specparam t_ctl_setup  = 1:1:1;  // Control signal setup time
      specparam t_ctl_hold   = 0:0:0;  // Control signal hold time


      //not in sdf file
      $width(posedge mclk, t_clk_high, 0, error_toggle);
      $width(negedge mclk, t_clk_low, 0, error_toggle);


      $setup(posedge data[0], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[1], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[2], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[3], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[4], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[5], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[6], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[7], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[8], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[9], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[10], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[11], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[12], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[13], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[14], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[15], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[16], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[17], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[18], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[19], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[20], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[21], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[22], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[23], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[24], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[25], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[26], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(posedge data[27], negedge mclk &&& (~wrb), t_data_setup, error_toggle);

      $setup(negedge data[0], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[1], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[2], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[3], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[4], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[5], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[6], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[7], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[8], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[9], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[10], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[11], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[12], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[13], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[14], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[15], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[16], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[17], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[18], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[19], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[20], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[21], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[22], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[23], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[24], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[25], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[26], negedge mclk &&& (~wrb), t_data_setup, error_toggle);
      $setup(negedge data[27], negedge mclk &&& (~wrb), t_data_setup, error_toggle);

      $hold(posedge mclk &&& (~wrb), posedge data[0], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[1], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[2], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[3], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[4], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[5], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[6], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[7], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[8], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[9], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[10], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[11], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[12], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[13], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[14], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[15], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[16], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[17], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[18], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[19], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[20], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[21], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[22], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[23], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[24], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[25], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[26], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), posedge data[27], t_data_hold, error_toggle);

      $hold(posedge mclk &&& (~wrb), negedge data[0], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[1], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[2], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[3], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[4], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[5], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[6], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[7], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[8], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[9], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[10], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[11], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[12], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[13], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[14], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[15], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[16], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[17], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[18], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[19], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[20], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[21], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[22], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[23], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[24], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[25], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[26], t_data_hold, error_toggle);
      $hold(posedge mclk &&& (~wrb), negedge data[27], t_data_hold, error_toggle);


      $setup(posedge a[0],negedge mclk, t_addr_setup, error_toggle);
      $setup(posedge a[1],negedge mclk, t_addr_setup, error_toggle);
      $setup(posedge a[2],negedge mclk, t_addr_setup, error_toggle);
      $setup(posedge a[3],negedge mclk, t_addr_setup, error_toggle);
      $setup(posedge a[4],negedge mclk, t_addr_setup, error_toggle);
      $setup(negedge a[0],negedge mclk, t_addr_setup, error_toggle);
      $setup(negedge a[1],negedge mclk, t_addr_setup, error_toggle);
      $setup(negedge a[2],negedge mclk, t_addr_setup, error_toggle);
      $setup(negedge a[3],negedge mclk, t_addr_setup, error_toggle);
      $setup(negedge a[4],negedge mclk, t_addr_setup, error_toggle);

      $hold(posedge mclk, posedge a[0], t_addr_hold, error_toggle);
      $hold(posedge mclk, posedge a[1], t_addr_hold, error_toggle);
      $hold(posedge mclk, posedge a[2], t_addr_hold, error_toggle);
      $hold(posedge mclk, posedge a[3], t_addr_hold, error_toggle);
      $hold(posedge mclk, posedge a[4], t_addr_hold, error_toggle);
      $hold(posedge mclk, negedge a[0], t_addr_hold, error_toggle);
      $hold(posedge mclk, negedge a[1], t_addr_hold, error_toggle);
      $hold(posedge mclk, negedge a[2], t_addr_hold, error_toggle);
      $hold(posedge mclk, negedge a[3], t_addr_hold, error_toggle);
      $hold(posedge mclk, negedge a[4], t_addr_hold, error_toggle);


      $setup(posedge wrb, negedge mclk, t_ctl_setup, error_toggle);
      $setup(negedge wrb, negedge mclk, t_ctl_setup, error_toggle);   
      $hold(posedge mclk, posedge wrb, t_ctl_hold, error_toggle);
      $hold(posedge mclk, negedge wrb, t_ctl_hold, error_toggle);

      $setup(posedge rdb, negedge mclk, t_ctl_setup, error_toggle);
      $setup(negedge rdb, negedge mclk, t_ctl_setup, error_toggle);
      $hold(posedge mclk, posedge rdb, t_ctl_hold, error_toggle);
      $hold(posedge mclk, negedge rdb, t_ctl_hold, error_toggle);


      if (!rdb) (negedge mclk => (data[0]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[1]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[2]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[3]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[4]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[5]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[6]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[7]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[8]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[9]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[10]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[11]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[12]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[13]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[14]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[15]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[16]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[17]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[18]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[19]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[20]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[21]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[22]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[23]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[24]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[25]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[26]+:mclk)) = (1,1,1);
      if (!rdb) (negedge mclk => (data[27]+:mclk)) = (1,1,1);

   endspecify


//---end timing---//


endmodule

8i8i9o9o

回复 1# 8i8i9o9o

那位帮帮忙，谢了

qqfishboy

不会~@~

swary

回复 1# 8i8i9o9o
首先，这是不可综合verilog。一般出现在模型中。
其次，verilog注释有两种方法：行注释和块注释
最后，data_tmp <= #1 -1，这是有符号数赋值给无符号数变量。-1是32bit的，在赋值过程中最后将-1的补码赋值给data_tmp，data_tmp应该是全1。这一点你可以自己动手仿真下。

星见

四楼正解，我刚动手仿真验证过