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发表于 2017-7-21 11:42:05
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我写的fpga端的发送程序:
程序如下:很简单,共3个文件,包含了激励文件。我的打算就是用单个ip核,自己发送自己接收,仿真正在进行,非常慢,一会了,还没出现显示波形的界面,希望大家看看,我的思路是否有错,哪里有错大家批评指正,没有人交流太痛苦。
第一个模块:NWRITE数据产生模块
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module srio_nwrite_gen(
input log_clk,
input log_rst,
input val_ireq_tready,
input link_initialized,
output reg val_ireq_tvalid,
output reg val_ireq_tlast,
output reg [7:0] val_ireq_tkeep,
output reg [63:0] val_ireq_tdata,
output [31:0] val_ireq_tuser
);
localparam [7:0] src_id=8'hff;
localparam [7:0] dest_id=8'hff;
localparam [3:0] NWRITE=4'd5;
localparam [3:0] TNWR =4'd4;
localparam [64*5-1:0] nwrite_instruction = {
// NWRITEs
{8'h66, NWRITE, TNWR,1'b0,2'b00,1'b0,8'h17,2'b00, 34'h300000000},
{64'h0000000000000000},
{64'h0000000000000001},
{64'h0000000000000002},
{64'h0000000000000003}};
wire [63:0] instruction[0:4];
genvar ii;
generate
for (ii = 0; ii <5; ii = ii + 1) begin : instruction_gen
assign instruction[ii] = nwrite_instruction[(ii+1)*64-1:ii*64];
end
endgenerate
reg [4:0] i;
//reg val_ireq_tlast;
always @(posedge log_clk or posedge log_rst)
if(log_rst)
begin
val_ireq_tvalid<=1'b0;
val_ireq_tdata<=64'd0;
val_ireq_tlast<=1'b0;
i<=4'd0;
end
else
begin
if(val_ireq_tready&&link_initialized)
begin
case(i)
0:
begin
val_ireq_tvalid<=1'b1;
val_ireq_tdata<=instruction[0];
val_ireq_tlast<=1'b0;
val_ireq_tkeep<=8'hff;
i<=i+1'b1;
end
1,2,3:
begin
val_ireq_tvalid<=1'b1;
val_ireq_tdata<=instruction;;
val_ireq_tlast<=1'b0;
i<=i+1'b1;
end
4:
begin
val_ireq_tvalid<=1'b1;
val_ireq_tdata<=instruction;
val_ireq_tkeep<=8'hff;
val_ireq_tlast<=1'b1;
i<=i+1'b1;
end
5:
begin
val_ireq_tlast<=1'b0;
i<=i+1'b1;
end
default:
begin
val_ireq_tvalid<=1'b0;
val_ireq_tdata<=64'd0;
val_ireq_tlast<=1'b0;
end
endcase
end
else
begin
val_ireq_tvalid<=1'b0;
val_ireq_tdata<=64'd0;
val_ireq_tlast<=1'b0;
end
end
assign val_ireq_tuser = {8'h0,src_id,8'h0, dest_id};
endmodule
第二个:第一个模块和ip核的连线
module top(
input sys_rst,
input sys_clkn,
input sys_clkp,
input phy_link_reset,
output link_initialized,
output port_initialized,
output log_rst,
output srio_txn0,
output srio_txp0
);
//wire log_rst;
wire [7:0] val_ireq_tkeep;
wire [31:0] val_ireq_tuser;
wire [63:0] val_ireq_tdata;
wire val_ireq_tvalid;
wire log_clk_out;
wire val_ireq_tready;
wire val_ireq_tlast;
srio_nwrite_gen U1(
.log_clk(log_clk_out),
.log_rst(log_rst),
.link_initialized(link_initialized),
.val_ireq_tlast(val_ireq_tlast),
.val_ireq_tvalid(val_ireq_tvalid),
.val_ireq_tkeep(val_ireq_tkeep),
.val_ireq_tuser(val_ireq_tuser),
.val_ireq_tready(val_ireq_tready),
.val_ireq_tdata(val_ireq_tdata)
);
//wire srio_txn0;
//wire srio_txp0;
rio ip_rio(
.log_clk_out(log_clk_out),
.log_rst_out(log_rst),
.s_axis_ireq_tdata(val_ireq_tdata),
.s_axis_ireq_tkeep(val_ireq_tkeep),
.s_axis_ireq_tvalid(val_ireq_tvalid),
.s_axis_ireq_tuser(val_ireq_tuser),
.s_axis_ireq_tready(val_ireq_tready),
.s_axis_ireq_tlast(val_ireq_tlast),
.link_initialized(link_initialized),
.port_initialized(port_initialized),
.phy_link_reset(phy_link_reset),
.srio_txn0(srio_txn0),
.srio_txp0(srio_txp0),
.srio_rxn0(srio_txn0),
.srio_rxp0(srio_txp0),
.sys_clkn(sys_clkn),
.sys_clkp(sys_clkp),
.sys_rst(sys_rst)
);
//rio ip_rio_rx(
// .log_clk_out(log_clk_out),
//// .s_axis_ireq_tdata(val_ireq_tdata),
//// .s_axis_ireq_tkeep(val_ireq_tkeep),
//// .s_axis_ireq_tvalid(val_ireq_tvalid),
//// .s_axis_ireq_tuser(val_ireq_tuser),
//// .s_axis_ireq_tready(val_ireq_tready),
//// .s_axis_ireq_tlast(val_ireq_tlast),
// .link_initialized(link_initialized),
// .port_initialized(port_initialized),
// .phy_link_reset(phy_link_reset),
//// .srio_txn0(srio_txn0),
//// .srio_txp0(srio_txp0),
// .srio_rxn0(srio_txn0),
// .srio_rxp0(srio_txp0),
// .sys_clkn(sys_clkn),
// .sys_clkp(sys_clkp),
// .sys_rst(sys_rst)
//);
endmodule
第三:激励文件
module sim(
input log_rst,
input sys_rst,
input phy_link_reset,
input sys_clkn,
input sys_clkp,
output link_initialized,
output port_initialized,
output srio_txn0,
output srio_txp0
);
top sim_top(
// .log_rst(log_rst),
.sys_rst(sys_rst),
.phy_link_reset(phy_link_reset),
.sys_clkn(sys_clkn),
.sys_clkp(sys_clkp),
.port_initialized(port_initialized),
.link_initialized(link_initialized),
.srio_txn0(srio_txn0),
.srio_txp0(srio_txp0)
);
reg sys_clkp_reg;
initial begin
sys_clkp_reg = 1'b0;
forever #40 sys_clkp_reg = ~sys_clkp_reg;
end
assign sys_clkn = ~sys_clkp_reg;
assign sys_clkp=sys_clkp_reg;
//initial begin
// system_rst_reg=1;b1;
// #2000
// system_rst_reg=1'b0;
//end
// reset generator
reg phy_link_reset_reg;
// reg log_rst_reg;
// initial begin
// log_rst_reg = 1'b1;
////// phy_link_reset_reg=1'b1;
// #1000
// log_rst_reg = 1'b0;
////// phy_link_reset_reg=1'b0;
// end
initial begin
// log_rst_reg = 1'b1;
phy_link_reset_reg=1'b1;
#1000
// log_rst_reg = 1'b0;
phy_link_reset_reg=1'b0;
end
reg sys_rst_reg;
initial begin
sys_rst_reg=1'b1;
#2000
sys_rst_reg=1'b0;
end
// assign log_rst=log_rst_reg;
assign phy_link_reset=phy_link_reset_reg;
assign sys_rst=sys_rst_reg;
endmodule |
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