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[招聘] 【AMD社招】SMTS ASIC Design Verification Engineer

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发表于 2016-10-21 16:50:09 | 显示全部楼层 |阅读模式

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AMD 超威半导体招聘SMTS asic Design Verification Engineer;请有意向者将简历发送到 Maggie1.Zhang@amd.com 以及 Cherry.Zhang@amd.com
Job Location: Beijing或者ShanghAI

Job description:
We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead SoC level function verification domains including:
1.        SoC DV testbench and infrastructure development and maintenance
2.        Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc.
3.        Implement directed and random test cases in C++/SV, as well as checkers and assertions
4.        Support integration and qualification of all the IPs for SoC
5.        Help to improve DV environment building flow

Requirement:
-   MS with 7+ or BS with 9+ years’ experience in ASIC/SoC design verification
-   DV lead experience is a must
-   Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both
-   Knowledgeable in C++ & SV development, familiar with scripting languages like Ruby/Perl/Makefile…
-   Strong problem solving and communication skills
-   Knowledge on computer architecture and PCIe devices is highly preferred
-   Good knowledge on verification methodologies like UVM is a big plus
-   Experience in power-aware verification is an asset
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