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楼主: petrel87

[求助] 输入端口激励问题,跪求

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发表于 2016-5-13 10:22:41 | 显示全部楼层
后仿需要load sdf,你先生成出来,再反标回去
 楼主| 发表于 2016-5-16 17:13:33 | 显示全部楼层
本帖最后由 petrel87 于 2016-5-16 17:17 编辑

回复 9# yaya126


   大神,我们的代码综合出来的网表还有个问题和sdf文件不匹配比如  reg [2:0] data   综合出来后就是data_0_,data_1_,data_2_,这样的格式,然后sdf里面要求的是data_reg[0],data_reg[1]这样的
请问什么语句是给内部端口命名的希望改成sdf文件匹配的,我把脚本再给您粘贴一下。麻烦了,指点小白
###################################### Current Design: TOP1553


# Load up design files
# uncomment one of the following
#analyze -format verilog TOP1553.v
analyze -format vhdl {if1553.vhd sysreg.vhd fifo.vhd transmitter.vhd rt1553.vhd receiver.vhd  encode10m.vhd encode.vhd  dpram.vhd  decode10m.vhd decode.vhd  TOP1553.vhd}


# Tell dc_shell the name of the top level module
elaborate TOP1553


# set a clock
create_clock {ext_clk clk}


# Check for warnings/errorsa
check_design -multiple_designs


# ungroup everything
ungroup -flatten -all


# flatten it all, this forces all the hierarchy to be flattened out
set_flatten true -effort high
uniquify


# compile the design
compile_ultra -area_high_effort_script
#compile_ultra -timing_high_effort_script
#compile_ultra


# Now that the compile is complete report on the results
report_area
report_timing
report_power


############################### begin: renaming section
# remove the following renaming section when not needed
# define the name rules for rename
define_name_rules verilog -remove_port_bus
define_name_rules verilog -remove_internal_net_bus


# name rule for nets
define_name_rules verilog -type net -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9 N" \
-replacement_char "_" \
-prefix "n"


# name rule for cells
define_name_rules verilog -type cell -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "u"


# name rule for ports
define_name_rules verilog -type port -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "p"


# change names of variables
change_names -rule verilog -hierarchy


################################ end: renaming section


# Write out the design
write -f verilog TOP1553 -output TOP1553_syn.v


remove_design -all


exit
发表于 2017-12-10 15:55:37 | 显示全部楼层
Thanks...
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