用tetramax生成atpg pattern时遇到的问题

mindy_xj

我的电路是只有一个时钟clkin，插入了2条扫描链，综合后通过tetramax生成atpg pattern没有任何问题，覆盖率为67.43%，但是经过布局布线后拿到的网表中就额外出现了175个时钟，此时钟和之前电路中的clkin时钟是同源的。
     再次生成atpg pattern时，工具会报出共有11个clock group，此时覆盖率为66.18%。问题在于生成出的测试pattern中，clkin和其它175个时钟在capture时不是同时assert的，而我进行测试仿真时是通过上层的clock源来控制shift和capture的，这个clock源为capture时，所有的175个额外的时钟都会被assert。这样测试必然会失败。
     我的想法是，怎么控制tetramax工具使其生成测试pattern时，所有的clock都同时被assert呢？
     从tetramax user guide中也没有找到关于clock_group的设置，所以将此问题发布到这里，请大家帮忙解决下。

Begin clock rules checking...
Clock rules checking completed, cpu time=0.09 sec.
The following clocks were identified as groupable with clock i_HCLKIN (0).
    PPU_CLK__L2_N59 (103)   PPU_CLK__L2_N75 (119)   PPU_CLK__L2_N78 (122)   PPU_CLK__L2_N107 (151)   PPU_CLK__L2_N123 (167)
    PPU_CLK__L2_N124 (168)   PPU_CLK__L2_N131 (175)   PPU_CLK__L2_N132 (176)   PPU_CLK__L2_N133 (177)   PPU_CLK__L2_N134 (178)
    PPU_CLK__L2_N135 (179)   PPU_CLK__L2_N138 (182)   PPU_CLK__L2_N146 (190)   PPU_CLK__L2_N147 (191)   PPU_CLK__L2_N148 (192)
    PPU_CLK__L2_N149 (193)   PPU_CLK__L2_N150 (194)   PPU_CLK__L2_N151 (195)   PPU_CLK__L2_N152 (196)   PPU_CLK__L2_N153 (197)
    PPU_CLK__L2_N154 (198)   PPU_CLK__L2_N155 (199)   PPU_CLK__L2_N156 (200)   PPU_CLK__L2_N157 (201)   PPU_CLK__L2_N158 (202)
    PPU_CLK__L2_N159 (203)   PPU_CLK__L2_N160 (204)   PPU_CLK__L2_N161 (205)   PPU_CLK__L2_N162 (206)   PPU_CLK__L2_N163 (207)
    PPU_CLK__L2_N164 (208)   PPU_CLK__L2_N165 (209)   PPU_CLK__L2_N166 (210)   PPU_CLK__L2_N167 (211)   PPU_CLK__L2_N168 (212)
    PPU_CLK__L2_N169 (213)   PPU_CLK__L2_N170 (214)   PPU_CLK__L2_N171 (215)   PPU_CLK__L2_N172 (216)   PPU_CLK__L2_N173 (217)
    PPU_CLK__L2_N174 (218)   PPU_CLK__L2_N175 (219)
The following clocks were identified as groupable with clock PPU_CLK__L2_N1 (45).
    PPU_CLK__L2_N108 (152)
The following clocks were identified as groupable with clock PPU_CLK__L2_N2 (46).
    PPU_CLK__L2_N114 (158)
The following clocks were identified as groupable with clock PPU_CLK__L2_N3 (47).
    PPU_CLK__L2_N136 (180)   PPU_CLK__L2_N142 (186)
The following clocks were identified as groupable with clock PPU_CLK__L2_N47 (91).
    PPU_CLK__L2_N125 (169)
The following clocks were identified as groupable with clock PPU_CLK__L2_N74 (118).
    PPU_CLK__L2_N81 (125)   PPU_CLK__L2_N105 (149)
The following clocks were identified as groupable with clock PPU_CLK__L2_N76 (120).
    PPU_CLK__L2_N140 (184)
The following clocks were identified as groupable with clock PPU_CLK__L2_N84 (128).
    PPU_CLK__L2_N137 (181)
The following clocks were identified as groupable with clock PPU_CLK__L2_N87 (131).
    PPU_CLK__L2_N103 (147)
The following clocks were identified as groupable with clock PPU_CLK__L2_N115 (159).
    PPU_CLK__L2_N122 (166)
The following clocks were identified as groupable with clock PPU_CLK__L2_N119 (163).
    PPU_CLK__L2_N139 (183)
Clock grouping results: #pairs=6357, #groups=11, #serial_pairs=2201, #disturbed_pairs=284, CPU time=2.61 sec.

mindy_xj

如果我进行如下设置，则i_HCLKIN会PPU_CLK__L2_N59同时assert，但是这样的话，会报warning，且覆盖率非常低，为26.49%.

add_pi_equivalences i_HCLKIN -same_polarity PPU_CLK__L2_N59
Begin clock rules checking...
Clock rules checking completed, CPU time=0.08 sec.
The following clocks were identified as groupable with clock i_HCLKIN (0).
    PPU_CLK__L2_N73 (117)   PPU_CLK__L2_N78 (122)   PPU_CLK__L2_N107 (151)   PPU_CLK__L2_N123 (167)   PPU_CLK__L2_N124 (168)
    PPU_CLK__L2_N131 (175)   PPU_CLK__L2_N132 (176)   PPU_CLK__L2_N133 (177)   PPU_CLK__L2_N134 (178)   PPU_CLK__L2_N135 (179)
    PPU_CLK__L2_N138 (182)   PPU_CLK__L2_N146 (190)   PPU_CLK__L2_N147 (191)   PPU_CLK__L2_N148 (192)   PPU_CLK__L2_N149 (193)
    PPU_CLK__L2_N150 (194)   PPU_CLK__L2_N151 (195)   PPU_CLK__L2_N152 (196)   PPU_CLK__L2_N153 (197)   PPU_CLK__L2_N154 (198)
    PPU_CLK__L2_N155 (199)   PPU_CLK__L2_N156 (200)   PPU_CLK__L2_N157 (201)   PPU_CLK__L2_N158 (202)   PPU_CLK__L2_N159 (203)
    PPU_CLK__L2_N160 (204)   PPU_CLK__L2_N161 (205)   PPU_CLK__L2_N162 (206)   PPU_CLK__L2_N163 (207)   PPU_CLK__L2_N164 (208)
    PPU_CLK__L2_N165 (209)   PPU_CLK__L2_N166 (210)   PPU_CLK__L2_N167 (211)   PPU_CLK__L2_N168 (212)   PPU_CLK__L2_N169 (213)
    PPU_CLK__L2_N170 (214)   PPU_CLK__L2_N171 (215)   PPU_CLK__L2_N172 (216)   PPU_CLK__L2_N173 (217)   PPU_CLK__L2_N174 (218)
    PPU_CLK__L2_N175 (219)
The following clocks were identified as groupable with clock PPU_CLK__L2_N1 (45).
    PPU_CLK__L2_N108 (152)
The following clocks were identified as groupable with clock PPU_CLK__L2_N2 (46).
    PPU_CLK__L2_N114 (158)
The following clocks were identified as groupable with clock PPU_CLK__L2_N3 (47).
    PPU_CLK__L2_N136 (180)   PPU_CLK__L2_N142 (186)
The following clocks were identified as groupable with clock PPU_CLK__L2_N47 (91).
    PPU_CLK__L2_N125 (169)
The following clocks were identified as groupable with clock PPU_CLK__L2_N74 (118).
    PPU_CLK__L2_N81 (125)   PPU_CLK__L2_N105 (149)
The following clocks were identified as groupable with clock PPU_CLK__L2_N75 (119).
    PPU_CLK__L2_N99 (143)
The following clocks were identified as groupable with clock PPU_CLK__L2_N76 (120).
    PPU_CLK__L2_N140 (184)
The following clocks were identified as groupable with clock PPU_CLK__L2_N84 (128).
    PPU_CLK__L2_N137 (181)
The following clocks were identified as groupable with clock PPU_CLK__L2_N87 (131).
    PPU_CLK__L2_N103 (147)
The following clocks were identified as groupable with clock PPU_CLK__L2_N115 (159).
    PPU_CLK__L2_N122 (166)
The following clocks were identified as groupable with clock PPU_CLK__L2_N119 (163).
    PPU_CLK__L2_N139 (183)
Clock grouping results: #pairs=6310, #groups=12, #serial_pairs=2179, #disturbed_pairs=281, CPU time=2.51 sec.

Begin deterministic ATPG: #uncollapsed_faults=83021, abort_limit=200...
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=1). (M179)
3            2852  80163         0/3/4     8.38%      3.04
Warning: 28 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
7            3447  76711         0/6/9    11.10%      5.72
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
10           2055  74648       0/11/12    12.72%      8.27
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
13           1580  73037       0/26/16    13.97%     10.74
Local redundancy analysis results: #redundant_faults=30, CPU_time=0.22 sec
Warning: 27 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
18           1966  71011       0/39/20    15.56%     13.55
Warning: 28 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=1). (M179)
22           1485  69489       0/57/27    16.73%     15.81
Warning: 28 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=1). (M179)
26            858  68583       1/82/30    17.41%     18.22
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
29            532  68013      1/103/34    17.83%     20.15
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
31           1099  66912      1/104/38    18.70%     22.26
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
34            924  65818      2/194/56    19.43%     26.34
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
37            393  65415      2/203/63    19.74%     28.11
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
38            235  65168      2/211/69    19.93%     29.67
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
41            521  64630      2/224/76    20.34%     31.37
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
43            261  64356      2/233/81    20.54%     33.02
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
45            153  64185      2/249/86    20.66%     34.51
Warning: 27 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
50            837  63335      2/260/95    21.32%     35.86
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
52            292  63027     2/270/102    21.55%     37.49
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=1). (M179)
54            199  62809     2/286/110    21.71%     39.14
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Untestable analysis status: #faults=10000, #UR_faults=50, #AU_faults=2892, #aborted=736, #inferred=0/0, time=14.97 sec ...
Untestable analysis results: #faults=14272, #UR_faults=145, #AU_faults=3326, #aborted=998, #inferred=0/0, time=20.07 sec
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
55            590  56737     2/300/128    22.21%     62.40
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
56            105  56632     2/300/139    22.29%     65.39
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
58            562  56070     2/300/149    22.73%     66.75
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
59            140  55930     2/300/153    22.84%     68.11
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
61            124  55806     2/300/161    22.94%     69.31
Warning: 28 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
65            771  55035     2/300/168    23.55%     70.30
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
66             82  54953     2/300/173    23.61%     71.25
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
67             92  54861     2/300/183    23.69%     72.15
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
68            291  54570     2/300/192    23.91%     73.02
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
70            226  54344     2/300/196    24.09%     73.73
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
71             34  54310     2/300/203    24.12%     74.43
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
73            181  54129     2/300/210    24.26%     75.18
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
74              9  54120     2/300/220    24.27%     76.64
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
75             59  54061     2/300/233    24.31%     77.97
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
76             33  54028     2/300/242    24.34%     78.70
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
77            457  53571     2/300/248    24.70%     79.36
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
78            237  53334     2/300/253    24.89%     79.98
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
79             16  53318     2/300/262    24.90%     80.60
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
81            303  53015     2/300/279    25.13%     81.91
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
82             63  52952     2/300/283    25.18%     82.46
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
84            345  52607     2/300/292    25.45%     83.06
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
85            120  52487     2/300/302    25.54%     83.70
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
86             81  52406     2/300/316    25.61%     84.87
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
87              6  52400     2/300/361    25.61%     86.21
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
90             46  52354     2/300/381    25.65%     87.19
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
92             14  52340     2/300/385    25.66%     87.61
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
93             27  52313     2/300/398    25.68%     88.06
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
95             59  52254     2/300/424    25.73%     89.30
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
96             71  52183     2/300/439    25.78%     89.84
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
97             41  52142     2/300/529    25.82%     93.28
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
99            245  51897     2/300/544    26.01%     94.12
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
100           106  51791     2/300/565    26.09%     94.87
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
101            74  51717     2/300/573    26.15%     95.25
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
102            38  51679     2/300/616    26.18%     96.81
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
103            67  51612     2/300/624    26.23%     97.18
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 31 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
104             9  51603     2/300/802    26.24%    100.59
Warning: 30 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
106             3  51600     2/300/814    26.24%    100.95
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 27 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=1). (M179)
111           186  51414     2/300/916    26.39%    104.06
Pattern merging terminated due to failure to achieve minimum merges per pass (10).
Warning: 27 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
116            78  51336     2/300/940    26.45%    104.21
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
119            49  51287     2/300/944    26.49%    104.27
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 32 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)
Warning: 29 patterns rejected due to 1 preclock constraint violations (ID=0, pat1=0). (M179)

   Uncollapsed Transition Fault Summary Report
-----------------------------------------------
fault class                     code   #faults
------------------------------  ----  ---------
Detected                         DT      33509
Possibly detected                PT        135
Undetectable                     UD      12138
ATPG untestable                  AU      41932
Not detected                     ND      51168
-----------------------------------------------
total faults                            138882
test coverage                            26.49%
-----------------------------------------------
            Pattern Summary Report
-----------------------------------------------
#internal patterns                         119
     #basic_scan patterns                   119
-----------------------------------------------
            CPU Usage Summary Report
-----------------------------------------------
Total CPU time                          104.57
-----------------------------------------------
write_patterns ARM7TDMIS_TC_CORE.stil -replace -internal -format stil
Warning: STIL patterns defaulted to serial simulation mode. (M473)
Patterns written reference 359 V statements, generating 115199 test cycles
End writing file 'ARM7TDMIS_TC_CORE.stil' with 119 patterns, File_size = 485108, CPU_time = 0.0 sec.
run_simulation
Begin good simulation of 119 internal patterns.
Simulation completed: #patterns=119, #fail_pats=0(0), #failing_meas=0(0), CPU time=0.02
run_fault_sim
Simulation performed for 51287 faults on circuit size of 32854 gates.
--------------------------------------------
#patterns     #faults     test      process
simulated  detect/active  coverage  CPU time
---------  -------------  --------  --------
32              0  51287    26.49%      0.03
Fault simulation completed: #patterns=119, CPU time=0.14
report_summaries
   Uncollapsed Transition Fault Summary Report
-----------------------------------------------
fault class                     code   #faults
------------------------------  ----  ---------
Detected                         DT      33509
Possibly detected                PT        135
Undetectable                     UD      12138
ATPG untestable                  AU      41932
Not detected                     ND      51168
-----------------------------------------------
total faults                            138882
test coverage                            26.49%
-----------------------------------------------
            Pattern Summary Report
-----------------------------------------------
#internal patterns                         119
     #basic_scan patterns                   119
-----------------------------------------------
report_faults -summary -verbose
   Uncollapsed Transition Fault Summary Report
-----------------------------------------------
fault class                     code   #faults
------------------------------  ----  ---------
Detected                         DT      33509
Possibly detected                PT        135
Undetectable                     UD      12138
ATPG untestable                  AU      41932
Not detected                     ND      51168
-----------------------------------------------
total faults                            138882
test coverage                            26.49%

mindy_xj

问题已经解决了，方法是将此网表包一个wrapper层，此wrapper层只有一个clock，并且用它驱动低层所有的clock。这样以此wrapper为top层来做atpg，生成的pattern中就仅需要控制一个clock。

努力的小七

过来学习学习

wangalt

回复 1# mindy_xj


    谢谢楼主，正好需要学习这个

出尘入世

看看错误，涨涨经验，敬谢不敏

2cky

感谢群主的经验分享。

hurrywork

求个 dftc和tetramax的脚本啊！！完全不知从哪儿下手