|
发表于 2014-9-3 11:48:55
|
显示全部楼层
Hi mikeppq,
No one use static comparator for SAR ADC, because in SAR ADC, comparator involve in a lot of circles of switching, so static comparator can not meet the specification. To check this thing, you just design a static comparator with clock frequency (comp) = fs(SAR) * 12 (I assumed you design asynchronous SAR ADC), and probe the average power consumption.
Your ADC is design in 0.18 um, it's possible that supply voltage = 1.8v, so there are a lot types of dynamic comparator can stand for 12bit with this supply.
When you use 3 stages of CDAC, it means you will use split capacitor, right? if it's the case, the problem is how you can do the layout for the bridge capacitor (example, Cb = 17/16 * Cunit).
The last thing is, if your design is for research, it's rare to see any papers had specification: 12b + sampling rate ~ 500kS/s. Normally, for biomedical devices: the res = 8-10b with sampling rate = 100k - 1M, and for wireless sensor network: res = 10-12b, fs = 1M-10M. |
|