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[讨论] Twin-well 和Triple-well指的是什么?[已解决]

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发表于 2012-4-10 10:37:51 | 显示全部楼层 |阅读模式

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本帖最后由 damonzhao 于 2013-1-15 10:18 编辑

有的工艺上说到Twin-well 和Triple-well。它们指的是什么?不同电压的阱,还是用了不同的layer?
发表于 2012-4-10 13:13:34 | 显示全部楼层
双井不用解释了吧, 三井是不是加上Deep Nwell?
发表于 2012-4-10 13:40:55 | 显示全部楼层
the twin well process is the process that contain 2 wells N and P.
the tripple well process that contain another well implemented in the wells.
like u have N well , implement a P well in it .
it is usually used for RF circuits to achieve good isolation.
for the tripple well process, Deep N-well was the third, usually. it can isolate p-well from P-
substrate, so the p-well would not be tied to ground, it can be any potential. this is very useful for some circuits.
for example, in the flash circuit, the tripple well process is must, because some circuits operate in the negative potential.
 楼主| 发表于 2012-4-10 14:23:48 | 显示全部楼层
回复 3# half_honey


    呵呵,解释的很详细呀
发表于 2013-1-15 10:06:09 | 显示全部楼层
In general MOS devices have 4 terminals D G S B.

B terminal [Bulk/Substrate] has an important role in MOS functionality. From the back-side of a MOS the substrate potential can affect the channel characteristics - it resembles very similar functionality of a Gate terminal of a FET [not a MOSFET but, a Field Effect Transistor], it is called back-gate. You want finer control of the back-gate - go get a triple-well MOS.

We call them isolated-MOS too - the reason being - electrically isolating the bulk node from global substrates.

Although it is not mandatory to keep Source & Substrate connection of a MOS be shorted together, there are design requirements, where the S,B needs to be locally shorted - please note, I did not mention yet - S,B shorted to VDD or GND. Keep it at whatever different potential from global VDD/VSS you need a triple-well process.

Triple well further reduces signal and noise coupling to and from substrate [OK, same as noise isolation].

Triple well might help addressing different potential requirements at IO ESD regions.

Well, somewhere I might have read something about virtual power switching [power-gating] using back-gate [not sure].

All such things are possible by using triple well structures.
-http://www.edaboard.com/thread137886.html

Well_structure_in_triple-well_process.JPG
简单来说,triple-well基本上是出于isolate考虑。
发表于 2013-1-15 10:25:15 | 显示全部楼层
发表于 2013-1-15 11:01:27 | 显示全部楼层
c
发表于 2013-1-15 11:02:26 | 显示全部楼层
发表于 2013-1-15 11:03:49 | 显示全部楼层
发表于 2013-1-15 13:15:28 | 显示全部楼层
ibm工艺喜欢叫triple nwell ,
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