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[原创] 65nmDC/DC 国外最新硕士论文有详细电路参数 仿真测试电路

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发表于 2011-11-26 14:06:46 | 显示全部楼层 |阅读模式

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Kisel Microelectronics AB to offer the opportunity to work  
本资料亮点 国外硕士论文 在公司实习完成的,该论文完全正向设计,包括外围电路参数计算 传递函数都有,所有的仿真波形 电路都有详细尺寸。 基于65nm工艺设计的 整个论文对电路原理的叙述相当少,但对于仿真电路的搭建却非常详细,该论文电路设计中缺乏必要地手算步骤 但对于当下在学校的自学的人仍不失一份非常优秀的范本。

Acknowledgements
  First of all I would like to thank Kisel Microelectronics AB to offer the opportunity to work on this  demanding and knowledge building  thesis work.  I must also thank  Johan Tingsborg, former CEO at Kisel, for showing trust in my abilities and for offering me this thesis work.

an integrated  high efficiency DC-DC converter implemented  in 65  nm CMOS.

Abstract
  This thesis work describes the  implementation perspective of an integrated  high efficiency DC-DC converter implemented  in 65  nm CMOS.  The implemented system employs the Buck converter topology to down-convert the input battery voltages. This converter offers its use as a power management unit in portable battery operated devices.   This thesis work includes the description  of  a basic Buck converter along with the various key equations  involved which describe the  Buck operation as well as are used to deduce the requirements for the  various internal building blocks of the system. A detailed
description of the operation as well as the design of each of the building blocks is included.     The implemented system can convert the input battery voltage in the range of 2.3 V to 3.6 V into an output supply voltage of 1.6 V. The system uses dual-mode feedback control to maintain the output voltage at 1.6 V. For the low load currents the PFM feedback control is
used and for the higher load currents the PWM feedback control is used. This converter can supply load currents from 0 to 300 mA with efficiency above 85%. The static line regulation of the system is < 0.1% and the load regulation of the system is < 0.3%. A digital soft-start circuit is implemented in  this system.  The system also includes the capability to trim the
output voltage in ~14 mV steps depending on the 4-bit input digital code.

An Integrated High Efficiency DC-DC Converter in 65 nm CMOS.pdf

8.25 MB, 下载次数: 1596 , 下载积分: 资产 -4 信元, 下载支出 4 信元

 楼主| 发表于 2011-11-26 14:08:05 | 显示全部楼层
自己顶一个 an integrated  high efficiency DC-DC converter implemented  in 65  nm CMOS.

Kisel Microelectronics AB to offer the opportunity to work on this  demanding and knowledge building  thesis work.
发表于 2011-11-26 22:36:53 | 显示全部楼层
绝对要顶的
发表于 2011-11-26 23:07:06 | 显示全部楼层
绝对要支持
发表于 2011-11-26 23:09:11 | 显示全部楼层
好东西
发表于 2011-11-27 13:37:38 | 显示全部楼层
正好要做这个
发表于 2011-11-28 10:12:12 | 显示全部楼层
thanks,
发表于 2011-11-28 11:17:18 | 显示全部楼层
thanks,
发表于 2011-11-28 12:12:01 | 显示全部楼层
绝对要顶
发表于 2011-11-28 12:23:50 | 显示全部楼层
nice...
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