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本帖最后由 angelweishan 于 2010-11-15 22:25 编辑
A 12-Bit, 75MS/s CMOS A/D Converter
Password decrypt
Hui Pan (hpan@icsLucla.edu)
Masahiro Segami (segami@icsLucla.edu)
Michael Choi (choi@icsLucla.edu)
Jing Cao (jcao@icsLucla.edu)
and Asad Abidi (abidi@icsl.ucla.edu)
Integrated Circuits and Systems Laboratory
Electrical Engineering Department
University of California, Los Angeles
Outline
I. Introduction: Research Objectives
II. Theoretical Investigations & Architecture Design
III. Cadence Design Environment
IV. Design of 6 & 7 bit Sub-ADCs
V. Design of Clock Generator and Output Buffers
VI. Design of T/H and Residue Amplifiers
VII. Whole Chip Verification and Layout
VIII. Conclusions |
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