关于自己写的DDR2控制器的问题

sxsyz2013

自己写的DDR2 控制器，在仿真突发长度为4的读写操作时，都出现列地址没有顺序的增加？
# DDR2_CTRL_wr_tb.ddr2.cmd_task: at time 2955000.0 ps INFO: Activate  bank 1 row 0101
# DDR2_CTRL_wr_tb.ddr2.cmd_task: at time 2960000.0 ps INFO: Write     bank 1 col 303, auto precharge 0
# DDR2_CTRL_wr_tb.ddr2.data_task: at time 2982500.0 ps INFO: WRITE @ DQS= bank = 1 row = 0101 col = 00000303 data = 04a0
# DDR2_CTRL_wr_tb.ddr2.data_task: at time 2985000.0 ps INFO: WRITE @ DQS= bank = 1 row = 0101 col = 00000300 data = 2020
# DDR2_CTRL_wr_tb.ddr2.data_task: at time 2987500.0 ps INFO: WRITE @ DQS= bank = 1 row = 0101 col = 00000301 data = 04a2
# DDR2_CTRL_wr_tb.ddr2.data_task: at time 2990000.0 ps INFO: WRITE @ DQS= bank = 1 row = 0101 col = 00000302 data = 2020
# DDR2_CTRL_wr_tb.ddr2.cmd_task: at time 3005000.0 ps INFO: Precharge All