TSMC CLN65Gplus

imhell

This section lists all of the foundry documents and technology files
used to design this product.

    o SRAM 6T 1.24um by 0.5um (0.62um^2) Cell
        - 065_LP_HC_M4_HVt_v10_demo_array_4x4.gds v1.0, July 21, 2006
        - Qualified by Foundry using deviated layout rules.
    o Design Rule Document For Layout, Antenna and electromigration
        - T-N65-CL-DR-001, V1.3 02-FEB-2007
    o GDS Layer Usage Description File:
        - Refer to Design Rule Document
          - T-N65-CL-LE-001, V1.2A 05-MAY-2006
    o DRC Command File
        - CALIBRE DRC COMMAND FILES --
                T-N65-CL-DR-001, V1.3a, 02-FEB-2007
        - CALIBRE ANTENNA DRC COMMAND FILES --
                T-N65-CL-DR-001, V1.3a, 02-FEB-2007
    o LVS Command File
        - T-N65-CL-LS-001-C1, V1.1, 03-MAY-06
    o Process Models
        - logic_spice
                T-N65-CL-SP-031-P1, v1.2, 23-MAR-2007(Logic models)
        - CLN65GPLUS_sr_v0d9.l, v0.9, July,12,2006(bitcell models)
    o Extractor Technology File
        - T-N65-CL-LS-001-E1, 20-MAR-2007

EDA Support
-----------
This section lists the EDA tools and versions supported for this
product release. This set of tools and versions corresponds
to arm Preliminary EDA Package 5.2

    * Cadence NC-Sim (verilog)
        - 5.1
    * Synopsys VCS (Verilog)
        - 7.2
    * Mentor ModelSim (Verilog)
        - 6.0
    * Simulation Model SDF Compatibility
        - SDF 2.1
    * Synopsys Design Compiler
        - 2006.06
    * Cadence RTL Compiler with .lib
        - 6.2
    * Synopsys PrimeTime (Static Timing, Delay Calculation)
        - 2006.06
    * Synopsys Power Compiler
        - 2006.06
    * Synopsys PrimePowerPower
        - 2006.06
    * Synopsys JupiterXT
        - 2006.06
    * Cadence SoC Encounter/First Encounter (Design Planning)
        - 6.2
    * Cadence SoC Encounter/NanoRoute (Place & Route)
        - 6.2
    * Synopsys Astro (VCLEF, .lib input)
        - 2006.06
    * Mentor Graphics Calibre (GDSII, CDL)
        - 2005.4_8.13
    * Adobe Acrobat Reader (PDF Documentation)
        - 5.0
    * Sun Solaris Operating System (Generator Software)
        - 8
    * Redhat Linux Operating System (Generator Software)
        - RHEL 3.0


Technology Implementation
-------------------------
This section provides information on items that may not be included
in the foundry documentation.

  Characterization Corners:
        - Timing and power views characterized at the following conditions:
           Typical      P/V/T = TT/1.0V/25C
           Fast@-40c    P/V/T = FF/1.1V/-40C
           Fast@0c      P/V/T = FF/1.1V/0C
           Slow         P/V/T = SS/0.9V/125C
           Slow         P/V/T = SS/0.9V/-40C
           Leakage      P/V/T = FF/1.1V/125C

http://www.4shared.com/file/iV37d2LW/fe_cln65gplus_rf-sp-adv-v50_20.html

sunrisewu

打不开链接？

hhuigy

打不开链接+1

chenycs

打不开链接+2

imhell

uploading alternate link for all.

imhell

Uploaded to new site.

http://depositfiles.com/files/fn8ns8nqt

deseetp

要好好學習一下

〖★★〗

Hold !

xxlist

回复 6# imhell


    只有Singal Ports SRAM Compiler，其它的呢?!
    谢谢！！

even_ryen

要翻墙