本帖最后由 雨丝 于 2019-1-29 14:58 编辑
Noise-Shaped & VCO-Based ADCs
20.1 A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving
30.5fJ/conv-step
20.2 A 40MHz-BW 320MS/s Passive-Noise-Shaping SAR ADC with Passive
Signal-Residue Summation in 14nm FinFET
20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved
4th-Order Noise-Shaping SAR ADC
20.4 An 8×-OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT ΔΣ Modulator Using 7b
Linearized Segmented DACs with Digital Noise-Coupling-Compensation
20.5 A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy
MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS
L. Qi1, A. Jain2, D. Jiang1, S-W. Sin1, R. P. Martins1,3, M. Ortmanns2
20.6 An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In
DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in
28nm LP for 802.11ax Applications
20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling
and Quantization Scheme in Backend Subranging QTZ |