关于VCO的论文

system2008

[size=-1]摘要 [size=-1]

[size=-1]PLL (Phase-Locked Loop) frequency synthesizers are used in wireless transceivers for frequency conversion. Recent directions in PLL frequency synthesizer research and development are to fully integrate PLL synthesizers in CMOS technology, to improve phase noise performance, and to operate wide range of frequency bands and channel bandwidths. Fully integration of synthesizers in CMOS technology is desired for low cost, low power consumption and small size in mobile wireless terminals. Low phase noise and high performance are required by digital modulation techniques which have been used in new generations of wireless standards for the efficient use of available frequency spectrum. Operation over a wide range of frequency bands and channel bandwidths are required to support migration and backward compatibility in the wireless standard evolution. This work explores wideband PLL frequency synthesizer design and implementation in CMOS technology with focus on integration of wideband VCOs (Voltage-Controlled Oscillators).hase noise of a PLL synthesizer is a major design consideration and integration issue. A PLL noise model is developed for noise optimization purposes. A SPICE implementation of the PLL noise model is presented and used in the design and optimization of PLLs for broadband wireless applications.;Wideband RF VCO design with sub-bands is investigated. Frequency planning, synthesizer architecture and technology considerations for integration are also explored for wideband VCO design. Band switching techniques for VCO tuning range are presented. Active VCO circuit topologies and resonator design are also presented.;Wideband PLL frequency synthesizers are designed and implemented for a multi-band/standard IEEE 802.11a/b/g WLAN radio in 0.18μm CMOS. Phase noise trade-offs for PLL design are explored in this application. Loop filter design in an integrated environment is also investigated. Development and design of a wideband VCO for this application is also presented. An auto calibration circuit is developed for the VCO tuning band selection.;Another application of the wideband PLL frequency synthesizer is designed and implemented for a fully integrated dual-mode frequency synthesizer for GSM and WCDMA standards in 0.5μm CMOS. A hybrid integer-N/fractional-N architecture is developed to meet the multi-standard requirements. A dual-band VCO is developed for this application.;Design and implementation of high performance RF VCO depends on the RF models of the devices. RF CMOS characterization and modeling techniques are explored. Microwave wafer measurement and calibration techniques are also investigated for CMOS technology. A test chip is developed in 0.5μm CMOS technology. CMOS technologies are evaluated for RF design.

system2008

[size=-1]摘要 [size=-1]

[size=-1]This dissertation investigates several design techniques to improve performance of LC Voltage-Controlled Oscillators (LC-VCO). First, AM-to-FM noise conversion by MOS device parasitics in differential LC-VCOs is examined and it is shown that there is an optimal oscillation amplitude where this conversion is minimum. The optimum amplitude for lowest AM-to-FM conversion also yields the lowest phase noise for this oscillator. The presented analysis is confirmed with simulation and measurement results for a 2-GHz differential nMOS VCO fabricated in a 0.25-mum BiCMOS process.;Next, a tail-current-shaping technique in LC-VCOs is presented to increase the oscillation amplitude and to reduce the phase noise while keeping the power dissipation constant. In this technique, the tail current is made large when the oscillator output voltage reaches its maximum or minimum value and when the sensitivity of the output phase to injected noise is the smallest; the tail current is made small during the zero crossings of the output voltage when the phase noise sensitivity is large. The operation and performance of the presented circuit is extensively analyzed and compared to an ideal pulse-biased technique. The presented analysis is confirmed with measurement results of two 2-GHz differential nMOS VCOs fabricated in a 0.25-mum BiCMOS process.;Then, a low-phase-noise quadrature LC-VCO with inherent tail-current shaping is presented. Two identical differential LC-VCOs are locked in quadrature with a capacitor connected between their common-source nodes. This capacitor further drives the oscillators into a tail-current-shaping mode, which increases their oscillation amplitude and reduces their phase noise. The stability of quadrature operation is analyzed and verified. A multiband 1.9-GHz differential nMOS quadrature LC-VCO prototype has been fabricated in a 0.25-mum BiCMOS process.;Finally, a fully integrated 0.024-mm2 6-GHz LC-VCO for 6+ Gbps high-speed serial (HSS) links in a 90-nm bulk CMOS is presented. It is comparable in size to ring oscillators, but it has better phase noise. It is less than one fifth the size of any LC-VCO reported to date at this frequency. Using a differential control, a very wide tuning range from 4.5 GHz to 7.1 GHz (45%) is achieved. Additionally, a circuit technique employing a differential inductor's center tap is presented to dynamically set the differential tune signals' common mode equal to the VCO's output common mode.

stoneduan

lz有没有 LOW phase noise low power的 CMOS full differential VCO？

fanjx

好好看看

fanjx

好东西就要顶

1973

希望和大家一起交流

meseasky

好东西,支持

meseasky

好东东,支持

joe_chen

haodongxi

nan123chang

回复 4# fanjx


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