求助：dc综合命令set_ideal_network，求大侠解释:)

fxty

回复 10# 潇洒的蛋壳Chris


   set_ideal_network 只是将net上的transition和delay默认设置为0，fix timing的时候是不会动到这个net的。但是我们还会设置max_fanout
它不管你是不是ideal的，只要扇出足够大他就会去优化。所以必须要给高扇出的net设置dont_touch属性。

潇洒的蛋壳Chris

回复 11# fxty

所以楼主的问题的解法就是不仅要设置如下的command:set_ideal_network rst_n1;
set_ideal_network rst_n2;
set_max_fanout 18 test;

因为rst_n是高扇出的net，还需要  set_dont_touch rst_n 咯。

姜思佳

受教了

xiaoyisimonguo

good response, learning

losenobody

摘自：
Synthesis
Commands
Version D-2010.03, March 2010

七点班车

fxty 发表于 2017-3-1 10:22
回复 10# 潇洒的蛋壳Chris

set_ideal_network的对象只能是port或者leaf cell（所谓leaf cell，可以理解成树状图的最后一集（树叶），在其下面再也没有包含其他cell）。楼主设置的点是hierachy的pin,DC会报一个warning，告诉你设置是invalid的。因此不管你怎么设置，都是没有用的。可以在input之后加一级buffer，然后再对buffer的输入或者输出set_ideal_network，这样子OK了。

amazingpang

除了buffer和invter，ideal 属性带不过去的

王之凡

#15楼的贴图，似乎应该理解为：ideal network带有dont touch属性，不会做时序优化。设置rst1和rst2为ideal network，按道理rst也是ideal network，理由是（参见Synthesis Commands）:
A combinational cell is marked as ideal if all of its input pins are either ideal or attached to a constant net (and other input pins are ideal). Objects with the case analysis attribute set are not treated as constant.
rst之所以会被DC插入buffer，应该是因为：
Propagation traverses through combinational cells but stops at sequential cells. If an ideal network overlaps a clock network, the clock timing overrides the ideal timing for the clock part of the network.
即ideal network到时序单元就终止了。所以rst的ideal属性不起作用。但是clock的ideal属性会起左右。
所以，需要设置rst为dont touch，dc才不插buffer。
  
不知道理解

徐海涛

sunhui_asic 发表于 2013-7-17 20:26
难道是set_ideal_network rst_n1这个属性不能穿过组合逻辑？但是如果rst_n1有ideal network属性的话，这根n ...

楼主你好，我看了一下您的描述和楼下的一些回答，感觉可能的原因并不是你的理解问题，可能是rst_n后面接的是一个时序cell，在官方原文中有这样的描述：A combinational cell is marked as ideal if all of its input pins are either ideal or attached to a constant net (and other input pins are ideal). Objects with the case analysis attribute set are not treated as constant .Propagation traverses through combinational cells but stops at sequential cells. If an ideal network overlaps a clock network, the clock timing overrides the ideal timing for the clock part of the network

徐海涛

sunhui_asic 发表于 2013-7-17 20:26
难道是set_ideal_network rst_n1这个属性不能穿过组合逻辑？但是如果rst_n1有ideal network属性的话，这根n ...

补上一段话，看完就懂了，官方解释完整版：A combinational cell is marked as ideal if all of its input pins are either idealor attached to a constant net (and other input pins are ideal). Objects with thecase analysis attribute set are not treated as constant.Propagation traverses through combinational cells but stops at sequential cells. Ifan ideal network overlaps a clock network, the clock timing overrides the idealtiming for the clock part of the network.In addition to disabling timing updates and timing optimizations, all cells and netsin the ideal network have the dont_touch attribute set