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Chapter 1 Introduction 1
Chapter 2 Implications of Short Channel Length 5
and Technology Dependence on Circuit Performance
2.1 DC Biasing 7
2.2 Small-signal Gain 12
2.3 Mismatch 14
2.4 Limits on Supply Voltage 20
2.5 Noise 21
2.6 High frequency Performance 26
2.7 Distortion 27
2.8 Summary of Use of Minimum Channel Lengths 28
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2.9 Technology-Dependent Circuit Performance 29
2.9.1 Op Amp with Current Mirror Load 31
2.9.2 Cascode Op Amp 34
2.10 Effect of Technology Scaling 37
2.11 min L -based Gain Stage with Constant Gain 39
2.12 min L -based Gain Stage for Maximum Gain 45
2.13 Weak Inversion Operation of the MOS device 48
2.14 Summary 53
Chapter 3 CMOS Implementation of the Gain Stages 55
in Minimum Channel Length
3.1 Negative Resistance Circuit 55
3.2 Gain Stage with Negative Resistance 58
and Constant Gain
3.3 Bulk Effects 63
3.4 Common-Mode Feedback (CMFB) Circuit 65
3.5 Gain Stage with Negative Resistance 67
and Maximum Gain
3.6 Bias Circuit 70
3.7 Constant Bias Current Generation 73
3.8 Summary 83
Chapter 4 Two-stage, Miller-Compensated Op Amp 84
with Constant Phase Margin
4.1 Op Amp Compensation 85
4.2 Slew Rate 89
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4.3 Input Referred Noise 89
4.4 Input Common-Mode Range (ICMR) 93
4.5 Power Supply Rejection Ratio (PSRR) 96
4.6 Simulation Results 98
4.6.1 Simulation Results of Op Amp OP1 99
4.6.2 Simulation Results of OP1 in 0.25 mm 101
CMOS Process
4.6.3 Simulation Results of OP1 in 0.18 mm 106
CMOS Process
4.6.4 Comparison of the Simulation Results 113
of OP1 in Two Different CMOS Processes
4.6.5 Simulation Results of Op Amp OP2 114
4.6.6 Simulation Results of OP2 in 0.25 mm 115
CMOS Process
4.6.7 Simulation Results of OP2 in 0.18 mm 120
CMOS Process
4.6.8 Comparison of the Simulation Results 125
of OP2 in Two Different CMOS Processes
4.7 Measurement Results 127
4.7.1 Measurement Results for 127
Matching of Devices
4.7.2 Bias Current Measurements 133
4.7.3 Measured Results of Op Amp OP2 138
4.7.4 Measured Results for OP2 in the 0.25 mm 144
CMOS Process
4.7.5 Measured Results for OP2 in the 0.18 mm 153
CMOS Process
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4.8 Summary of Lmin -based Design 156
Chapter 5 Technology-Independent Op Amp Design 158
with Constant Gain Bandwidth and Phase Margin
5.1 Generation of Technology-Independent gm 159
5.2 Gain Stage of OP3 165
5.3 Compensation of OP3 167
5.4 Simulation Results 172
5.4.1 Simulation Results of OP3 in the 0.25 mm 172
CMOS Process
5.4.2 Simulation Results of OP3 in the 0.18 mm 177
CMOS Process
5.4.3 Comparison of the Simulation Results 182
of OP3 in Two Different CMOS Processes
5.5 Measurement Results 185
5.5.1 Measured Results of OP3 in the 0.25 mm 186
CMOS Process
5.5.2 Measured Results of OP3 in the 0.18 mm 192
CMOS Process
5.6 Summary 199
Chapter 6 Buffered Op Amps 201
6.1 Current Feedback m g Boosted PMOS Source 202
Follower with NMOS current mirror sink
6.2 Current Feedback m g Boosted PMOS Source 213
Follower with Resistor-NMOS sink
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6.3 Current Feedback m g Boosted Push-Pull 223
Source Follower
6.4 Buffered OP2 228
6.4.1 Simulation Results of Buffered OP2 229
6.4.2 Measurement Results of Buffered OP2 231
6.5 Buffered OP3 237
6.5.1 Simulation Results of Buffered OP3 237
6.5.2 Measurement Results of Buffered OP3 239
6.6 Future Work 252
6.7 Summary |
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