Analog Simulations of High-Speed Serial Chip-to-Chip Links with HSPICE

sysclock

Analog Simulations of High-Speed Serial Chip-to-Chip Links with HSPICE

kevinwjs

QQQQQQQQQQQQQQ

fanjx

值得借鉴值得借鉴

digito77

感謝感謝!! 下來看看

mk2708123

顶顶顶

nesta

Christoph Werner (Nokia Siemens Networks) and
David Sebastio (Texas Instruments Ltd)

ABSTRACT
In recent years serial data transmission between different chips has been extended to rates of
multi gigabits per second. We performed analog simulations with the circuit simulator HSPICE
for the entire transmission path from the modules inside the transmitting chip to the clock-datarecovery
modules in the receiver, including also models for the packages, striplines and
connectors on the PCB boards.
The influence of board layout as well as the settings of de-emphasis and equalization parameters
has been investigated to achieve a bit error free data transmission. A variety of applications were
studied including Serial Rapid IO links of up to 3.125 Gbps, DDR2 memory devices, and CPRI
links of 2.5 Gbps inside mobile radio base stations.
The chips investigated in this study include state of the art DSP, FPGA, ASIC and Memory
devices, with encrypted HSPICE models for the transceiver modules provided by the chip
vendors. Package and transmission lines were modeled in HSPICE using the W-model and the
two-dimensional field solver utility.
Signal integrity effects studied in our investigation include:
- Setting of swing amplitude and de-emphasis in the transmitter
- Optimized setting of equalization parameters for low and high frequency
- Reflection and loss of signal amplitude at non perfectly terminated transmission lines
- Jitter and distortion of clock signals and their impact on data recovery
- Voltage drop and noise on the power supply

liuzhieetop

:victory:

muyangtong

rtm

下来学习学习

yuxi

很好，谢谢