JESD204B IP core

mylove8725

求助，需要JESD204B的IP core，哪里可以买到啊？

passion1

回复 1# mylove8725


   楼主找到了吗

designstart

Feature Availability Comment
General Features
Standard JEDEC JESD204C December 2017
Versions Transmitter/Receiver Optional
Technology Verilog RTL For ASIC, ASSP, FPGA
Encodings 64b/66b, 64b/80b Compliant with the JESD204c standard
Line Rates Up to 32Gbps Configurable
Lanes 1 - 24 Configurable
Number of Converters per
device
1 – 32 Configurable
Converter resolution 8 – 32 Configurable
Total number of bits per sample 8, 12, 16, 20, 24, 28, 32 Configurable
Control Word 0 - 1 Configurable
Control bits per sample 0 - 3 Configurable
HD mode Supported Configurable
Frame Size 1-32 Configurable
Extended Multiblock Size 1-127 Configurable
Subclasses 0, 1
Configuration Standard CPU interface
Debug Yes Debug signals can be provided
Receiver/Transmitter
PCS (8b/10b coding) Yes
PCS (64b/66b coding) Yes
PCS (64b/80b coding) Yes
Scrambling Yes Optional for 8b10b- included per default for
the other encoding
Interfaces
Sample interface JESD_N_MAX*JESD_NO_CONVERTERS*JESD_SAMPLES_ON_IF
Mapper interface 64*JESD_NO_LANES-bits
SERDES interface (excl. PHY) 40, 64, 66, 80 bits encoded
CPU interface 32 bits
Deliverables
Product Brief Yes
User Manual Yes
Verification Guide Yes
Regression Test Environment Yes Available through partners
Test Cases and Test Reports Yes Compliance according to verification
specification