求教大神！xilinx,GTX,7 Series FPGAs Transceivers Wizard数据传输问题

scratdqy · 发表于 2015-7-28 18:04:47

本帖最后由 scratdqy 于 2015-7-28 18:09 编辑

向各位大神求助GTX问题！！用xilinx的Vivado中的7 Series FPGAs Transceivers Wizard v3.5 在VIRTEX-7 VC707板上用光口传输数据，一块板自收发的时候，传输它example design中自带的以16组数据（每组数据为80bits,其中有32位全零，32位数据，以及16位的周期标志）为周期的数据的时候正确，但是换为以57组数据为周期的时候就会偶尔大约十几个周期在一个周期的头数据处出现一次错误，请问大神们应该如何修改？这个IP核与传输数据周期有关的地方在哪里？如何调整呢？多谢各位啦！

本人小白，还请大神们详细指点哈~

anovickis · 发表于 2015-7-29 01:23:36

which example design are you working with ?
http://xgoogle.xilinx.com/search ... true&getfields=*&q=+inmeta

ocument%2520Type%3DExample%2520Designs+inmeta:Board%2520and%2520Kit%3DVirtex%252D7%2520FPGA%2520VC707%2520Evaluation%2520Kit+inmeta

ocument%2520Class%3DDocument+inmeta

roduct%2520Type%3DBoards%2520and%2520Kits&dnavs=inmeta

ocument%2520Type%3DExample%2520Designs+inmeta:Board%2520and%2520Kit%3DVirtex%252D7%2520FPGA%2520VC707%2520Evaluation%2520Kit+inmeta:Document%2520Class%3DDocument+inmeta

roduct%2520Type%3DBoards%2520and%2520Kits

anovickis · 发表于 2015-7-29 01:24:10

which example design are you working with ?
http://xgoogle.xilinx.com/search ... true&getfields=*&q=+inmeta

ocument%2520Type%3DExample%2520Designs+inmeta:Board%2520and%2520Kit%3DVirtex%252D7%2520FPGA%2520VC707%2520Evaluation%2520Kit+inmeta

ocument%2520Class%3DDocument+inmeta

roduct%2520Type%3DBoards%2520and%2520Kits&dnavs=inmeta

ocument%2520Type%3DExample%2520Designs+inmeta:Board%2520and%2520Kit%3DVirtex%252D7%2520FPGA%2520VC707%2520Evaluation%2520Kit+inmeta:Document%2520Class%3DDocument+inmeta

roduct%2520Type%3DBoards%2520and%2520Kits

anovickis · 发表于 2015-7-29 01:24:37

which example design are you working with ?
http://xgoogle.xilinx.com/search?output=xml_no_dtd&ie=UTF-8&oe=UTF-8&client=support&proxystylesheet=support&site=Answers_Docs&filter=0&resultsView=category&tab=bk&num=1000&sortBy=displayOrder&show_dynamic_navigation=1&sort=date%3AD%3AR%3Ad1&documentClass=Document&requiredfields=-Archived%3Atrue&getfields=*&q=+inmeta

ocument%2520Type%3DExample%2520Designs+inmeta:Board%2520and%2520Kit%3DVirtex%252D7%2520FPGA%2520VC707%2520Evaluation%2520Kit+inmeta

ocument%2520Class%3DDocument+inmeta

roduct%2520Type%3DBoards%2520and%2520Kits&dnavs=inmeta

ocument%2520Type%3DExample%2520Designs+inmeta:Board%2520and%2520Kit%3DVirtex%252D7%2520FPGA%2520VC707%2520Evaluation%2520Kit+inmeta:Document%2520Class%3DDocument+inmeta

roduct%2520Type%3DBoards%2520and%2520Kits

huangxjmail · 发表于 2015-7-29 08:55:13

问题解决了吗？我也遇到了类似的问题，我用xaui core接收数据时，接收固定包长的帧没有错，接收随机包长的帧就会大概率的在包尾出出现一次错误

IC_creature · 发表于 2015-7-29 11:23:02

光接口压根儿没反应的，有什么好的建议？

greenpine · 发表于 2015-7-29 14:16:34

是否用ibert测试过硬件的稳定性

anovickis · 发表于 2015-7-30 01:35:05

(And sorry for previous multiple post)
yes I would make ibert first and check results to validate physical link
are you running on vc707 or your target ?

scratdqy · 发表于 2015-7-30 13:03:14

本帖最后由 scratdqy 于 2015-7-30 13:13 编辑

我用的example design就是由7 Series FPGAs Transceivers Wizard v3.5 生成的。然后是在一块VIRTEX-7 VC707板上用光口传输数据，自发自收。

以16,32或者64组数据为一个周期传输时没有错误（硬件稳定性就应该没有问题吧），但是以57组数据为一个周期时就会出错。。。请问大神们是这个IP核对传输数据周期有限制吗？？只能16，32或64？？但是我在手册里面没有找到相关说明啊？？我传两个手册恳请大神们指出！

pg168-gtwizard.pdf (7.26 MB, 下载次数: 32 )

ug476_7Series_Transceivers.pdf (14.1 MB, 下载次数: 43 )

scratdqy · 发表于 2015-7-30 13:31:23

本帖最后由 scratdqy 于 2015-7-30 13:38 编辑

回复 2# anovickis

I'm working with the example design generated by 7 Series FPGAs Transceivers Wizard v3.5. And run it on VIRTEX-7 VC707. Use 16,32 or 64 groups of data as a cycle is OK, but for 57 groups of data as a cycle is wrong. Is it a specific limit of the IP core?
Please look over my latest post~

THANKS A LOT!!

[求助] 求教大神！xilinx,GTX,7 Series FPGAs Transceivers Wizard数据传输问题

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