版图中通孔的个数会不会影响寄生电容？

hhlunar

请问各位大神，管子的通孔打的越多，寄生电阻越小，会不会意味着寄生电容更大呢？

semico_ljj

和Cap没有关系吧

liiru

通孔多了会使寄生电容增加的，高速信号的路径，通孔不要太多太密！

liiru

其实最好的办法就是你做一小块电路去比较一下，实践得真知

xuehaiwuya

应该是通孔多，寄生电容变小，主要是金属板重叠面积减小，寄生减小

julise

A ---------------
      |           |      
C1==       R1
      |           |
      |  - || -  |
      |    C3   |
C2==        R2
      |          |
      |          |
B ---------------

dumped eqvalent impedance between plate A and B.

R1 and R2 is resistance of via.
C1 and C2 is vertical parastice capacitance between A and B.
C3 is parastice laternal capacitance between several via.

Premise : another via pattern do not have to exist around AB overlap area.
the More via, the more C3.
But, idealy for proper frequency, if R1=R2 and C1=C2,
then we can say V(C)=V(D).
So we can ignore C3 for simplicity.

if R1=R2=R/2, C1=C2=C/2
Between A and B, equvalent impedance Z = R || (1/sC)


R1 = R0/k (k : the number of via)
resistance will be decrease with directly propotitionnal to the nubmer of via.
C1 = C0*(1-k*r) ( r : via area / original overlap area )
capacitance will be propotional with overlap area between A and B.
But it must substract via area.So as more via, as capacitance will be decrease.

Z = R / (1 + sCR) -> low pass function.

Fc = 1/(2pi*Tc)
     Tc = R*C = R0*C0*(1/k-r)

As more via, TC decrease and then Fc will be increase.
So for high frequecy, we need more via and small area of A and B.

fuyibin

通孔多了会使寄生电容增加的，高速信号的路径，通孔不要太多太密！
liiru 发表于 2012-12-31 16:51

                               
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没听说过这种理论，via当然多一点好，阻抗小，电容增加？这个忽略不计。

semico_ljj

via 和寄生电感有点关系，Cap可以忽略

lihaixi

回复 6# julise


    分析的很好，总体而言，via越多，寄生电阻越小，寄生电容越小；

nobody_yet

自己画几个通孔密度不同的版图，用电磁场工具仿真即可验证。