OpenMIPS成长roadmap

vlsi1217

期待Verilog的实践版本和freertos~

504472832

回复 1# leishangwen


   你好，lz，能不能了解下OpenMIPS各个版本的资源占用情况，和85C下STA的结果，谢谢！

leishangwen

回复 22# 504472832


这是VHDL实践版的资源占用情况  
  

这是quartus_Sta 85C的情况

Info: Command: quartus_sta openmips --model=slow
Info: qsta_default_script.tcl version: #4
Info: Using timing model slow
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Critical Warning: Synopsys Design Constraints File file not found: 'openmips.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
    Info: create_clock -period 1.000 -name clk clk
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -22.627
    Info:     Slack End Point TNS Clock
    Info: ========= ============= =====================
    Info:   -22.627    -25492.117 clk
Info: Worst-case hold slack is 0.391
    Info:     Slack End Point TNS Clock
    Info: ========= ============= =====================
    Info:     0.391         0.000 clk
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is -1.627
    Info:     Slack End Point TNS Clock
    Info: ========= ============= =====================
    Info:    -1.627     -2821.430 clk
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 232 megabytes
    Info: Processing ended: Wed Feb 26 20:25:03 2014
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:04

verilog HDL实践版还没出来

leishangwen

回复 21# vlsi1217


    亲，openmips暂时没计划移植freertos噢

504472832

回复 23# leishangwen


   非常感谢,

李九阳

赞，坐等verilog版

shixha

超级棒!

leishangwen

回复 27# shixha


    欢迎到http://blog.csdn.net/leishangwen?viewmode=contents查看详细，会陆续上传

oldbeginner

回复 28# leishangwen


    十天学习 verilog 版 笔记会有吗？ 类似VHDL版的，由小变大的模块讲解方式。

gyf1989

不错的分享，持续关注中