Synopsys内推（武汉）大量职位

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Job Description and Requirements

R&D Engineer Sr I (Design & Directed Verification) Job role: The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Design & Directed Verification domain. The position offers learning and growth opportunities in Synopsys’ new Design Center at Wuhan. Job Responsibilities - - Be an individual contributor in the Design Tasks – RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc. - Create/ work on designs using Low Power Design Methodology. - May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity functions/ product features for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI - Creates deliverables which do not require close review or supervision by a Senior Technical Lead. - May learn to do technical review of RTL Code of small complexity. - The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs. - The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide. Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas: - Design of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. - Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI - Hands on experience with creating micro-architecture/ detailed design from Functional Specifications for small/ medium design complexity. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc. - Hands on experience with Verilog/ System Verilog coding and Simulation tools - Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background - Knowledge of C - Experience with Perforce or similar revision control environment - Knowledge of Perl/Shell scripts. In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills. Candidate may be required to handle complex/ abstract problems

whitetiger

回复 1# whitetiger


   

Job Description and Requirements

R&D Engineer Sr I (Design & Directed Verification) Job role: The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Design & Directed Verification domain. The position offers learning and growth opportunities in Synopsys’ new Design Center at Wuhan. Job Responsibilities - - Be an individual contributor in the Design Tasks – RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc. - Create/ work on designs using Low Power Design Methodology. - May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity functions/ product features for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI - Creates deliverables which do not require close review or supervision by a Senior Technical Lead. - May learn to do technical review of RTL Code of small complexity. - The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs. - The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide. Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas: - Design of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. - Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI - Hands on experience with creating micro-architecture/ detailed design from Functional Specifications for small/ medium design complexity. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc. - Hands on experience with Verilog/ System Verilog coding and Simulation tools - Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background - Knowledge of C - Experience with Perforce or similar revision control environment - Knowledge of Perl/Shell scripts. In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills. Candidate may be required to handle complex/ abstract problems

whitetiger

回复 2# whitetiger


   

R&D Engineer Sr I (Verification – High Level Verification)

Job role:

The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. The position offers learning and growth opportunities in Synopsys’ new Design Center at Wuhan.

Job Responsibilities -

-
Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc.

-
May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity modules in the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI

-
Creates deliverables which do not require close review or supervision by a Senior Technical Lead.

-
May learn to do technical review of TE Code of small complexity.

-
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment, at least for small/ medium complexity features of the protocol/ product specs.

-
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

-
Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.

-
Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI

-
Hands on experience with creating detailed design of certain simple components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM.

-
Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts

-
Experience with Perforce or similar revision control environment

-
Knowledge of Perl/Shell scripts.

In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills. Candidate may be required to handle complex/ abstract problems

whitetiger

回复 3# whitetiger


   

R&D Engineer Sr I (Verification – High Level Verification)

Job role:

The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. The position offers learning and growth opportunities in Synopsys’ new Design Center at Wuhan.

Job Responsibilities -

-
Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc.

-
May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity modules in the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI

-
Creates deliverables which do not require close review or supervision by a Senior Technical Lead.

-
May learn to do technical review of TE Code of small complexity.

-
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment, at least for small/ medium complexity features of the protocol/ product specs.

-
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

-
Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.

-
Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI

-
Hands on experience with creating detailed design of certain simple components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM.

-
Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts

-
Experience with Perforce or similar revision control environment

-
Knowledge of Perl/Shell scripts.

In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills. Candidate may be required to handle complex/ abstract problems

whitetiger

回复 4# whitetiger


   

R&D Engineer Sr I (Verification – High Level Verification)

Job role:

The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. The position offers learning and growth opportunities in Synopsys’ new Design Center at Wuhan.

Job Responsibilities -

-
Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc.

-
May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity modules in the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI

-
Creates deliverables which do not require close review or supervision by a Senior Technical Lead.

-
May learn to do technical review of TE Code of small complexity.

-
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment, at least for small/ medium complexity features of the protocol/ product specs.

-
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

-
Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.

-
Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI

-
Hands on experience with creating detailed design of certain simple components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM.

-
Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts

-
Experience with Perforce or similar revision control environment

-
Knowledge of Perl/Shell scripts.

In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills. Candidate may be required to handle complex/ abstract problems

whitetiger

回复 5# whitetiger


   

R&D Engineer Sr I (Verification – High Level Verification)

Job role:

The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. The position offers learning and growth opportunities in Synopsys’ new Design Center at Wuhan.

Job Responsibilities -

-
Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc.

-
May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity modules in the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI

-
Creates deliverables which do not require close review or supervision by a Senior Technical Lead.

-
May learn to do technical review of TE Code of small complexity.

-
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment, at least for small/ medium complexity features of the protocol/ product specs.

-
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

-
Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.

-
Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI

-
Hands on experience with creating detailed design of certain simple components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM.

-
Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts

-
Experience with Perforce or similar revision control environment

-
Knowledge of Perl/Shell scripts.

In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills. Candidate may be required to handle complex/ abstract problems

whitetiger

回复 6# whitetiger


   R&D Engineer, Sr II (Design and Directed Verification)

Job role:


The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Senior Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Design and Directed Verification domain.


Job Responsibilities -


-   Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the design.


-   Be an individual contributor in the Design Tasks – RTL coding of design, synthesis, CDC analysis, debug, verification coverage improvement in directed Verilog test environment, if needed, etc.


-   May contribute to technical review of RTL Code, VTB Code, etc of small/ medium complexity.


-   May contribute to technical process and quality improvement to achieve high quality deliveries


-   May be expected to Solve complex/ abstract problems


-   The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases.


-   May need to interact with customers to discuss/ understand customers’ specification requirements, if needed for small/ medium complexity.


-   The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.


Must have BSEE in EE with 10+ years of relevant experience or MSEE with 8+ years of relevant experience in the following areas:


-   Design of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.


-   Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI


-   Hands on experience with creating micro-architecture/ detailed design from Functional Specifications. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.


-   Hands on experience with Verilog/ System Verilog coding and Simulation tools


-   Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background


-   Knowledge of C


-   Experience with Perforce or similar revision control environment


-   Knowledge of Perl/Shell scripts.


-   Exposure to quality processes in the context of IP design and verification is an added advantage


-   Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.

whitetiger

回复 7# whitetiger


   

R&D Engineer, Sr II (Verification)

Job role:

The candidate will be part of the Solutions Group at our new Design Center at Wuhan, China. This is a Senior Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain.

Job Responsibilities -

-
Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI/ MIPI

-
Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc.

-
May contribute to technical review of TE Code of small/ medium complexity.

-
May contribute to technical process and quality improvement to achieve high quality deliveries

-
May be expected to Solve complex/ abstract problems

-
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment.

-
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

-
Solve complex/ abstract problems

-
May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers.

Must have BSEE in EE with 10+ years of relevant experience or MSEE with 8+ years of relevant experience in the following areas:

-
Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.

-
Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI

-
Hands on experience with creating detailed design of certain components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM.

-
Hands on experience with System Verilog/ VERA/ Specman coding and Simulation tools; Knowledge of C++/ OOPs Concepts

-
Experience with Perforce or similar revision control environment

-
Knowledge of Perl/Shell scripts.

-
Exposure to quality processes in the context of IP design and verification is an added advantage

-
Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.

In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills

whitetiger

回复 8# whitetiger


   Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multi-dimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results.

Has a strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience of CAD tool development are required.

Typically requires a minimum of 2 years of related experience. Developing professional expertise, applies company policies and procedures to resolve a variety of issues. Has working knowledge of work area and general proficiency with tools, systems, and procedures required to accomplish the job. Exercises judgment within defined procedures and practices to determine appropriate action. Receives general instructions on routine work, detailed instructions on new assignments. Implementations and solutions are reviewed for accuracy and overall adequacy. Builds productive internal/external working relationships. Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.

whitetiger

回复 9# whitetiger


   Responsibilities

·
Enhance and maintain the current and future ARC compiler toolchain products. These include compilers, Eclipse IDE, debuggers, linkers/assemblers, Java GUIs, Linux and real-time operating systems, and processor simulation tools.

·
Interact with tool engineers and other teams to define, implement and deliver new product features to help Synopsys customers write their software

·
Perform various benchmarking and engineering testing tasks to improve overall product quality

·
Assist product marketing and product support teams with pre- and post-sales situations

Requirements

·
Some knowledge or exposure to the internals of software development tools e.g. compiler parsing and back-end code generation, Java GUIs, or open source tool projects

·
Programming skills in C++, C and optionally Java

·
Professional experience though the software engineering lifecycle i.e. design, coding, debugging, testing, delivery, support

• Excellent written and verbal skills including:
  
  • Written and spoken English
  • Detailed status reporting
  • Ability to present results to management
• BSCS degree or equivalent, MSCS preferred

Required Personality Skills

• Team player with good communications skills keen to work in a global development environment

• Self-motivated

Helpful qualifications

• Experience with embedded systems or systems software

·
Exposure to assembly language programming and instruction-set architectures

• Experience of working within a multi-site global development team