hspice:Undefined parameter or function definition

loveheihei · 发表于 2012-8-17 09:30:17

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

用NCX调用的Hspice仿真，遇到错误提示：
netlist: /home/mytools/ycp_work/liberty/sim_data/typical_1v2c25/DFFRX1/pCK_0020r/pCK_0020r.sp
Undefined parameter or function definition "dtox_n12" for n12. Please enter a defined name.

Error: Simulating netlist [/home/mytools/ycp_work/liberty/sim_data/typical_1v2c25/DFFRX1/pCK_0020r/pCK_0020r.sp] fails for cell DFFRX1. (NCXFL-5)

netlist: /home/mytools/ycp_work/liberty/sim_data/typical_1v2c25/DFFRX1/pCK_0008r/pCK_0008r.sp
Undefined parameter or function definition "dtox_n12" for n12. Please enter a defined name.

Error: Simulating netlist [/home/mytools/ycp_work/liberty/sim_data/typical_1v2c25/DFFRX1/pCK_0008r/pCK_0008r.sp] fails for cell DFFRX1. (NCXFL-5)

不知道什马情况？？？
有人遇到过吗？求解阿

loveheihei · 发表于 2012-8-17 09:31:37

发现所有的错误提示都有 Undefined parameter or function definition "dtox_n12" for n12. Please enter a defined name.

cheming0947 · 发表于 2013-8-31 21:53:56

本帖最后由 cheming0947 于 2013-8-31 21:56 编辑

我也是用NCX要寫出cell library時，遇到了下面的問題，
解了很久但不知道問題在哪邊，請問有高手能夠幫忙嗎？
謝謝

----------------------------------------------------------
Sat Aug 31 21:09:27 2013
checking job status... 0 nets queued, 1 jobs running, 1 pending, 0 done.

Sat Aug 31 21:09:58 2013
checking job status...
Warning: Fail to run job for /home/Lab333a/Desktop/NCX_problem_x64/ncx_ERFF/sim_dir/lib/erff_slow_ncx/ERFF/mCK_CK_0000f/mCK_CK_0000f.sp
Warning: Fail to run job for /home/Lab333a/Desktop/NCX_problem_x64/ncx_ERFF/sim_dir/lib/erff_slow_ncx/ERFF/dERFF_0029/dERFF_0029.sp
done.

job [0] [11 simulations]
Warning: Recheck /home/Lab333a/Desktop/NCX_problem_x64/ncx_ERFF/sim_dir/lib/erff_slow_ncx/ERFF/mCK_CK_0000f/mCK_CK_0000f.acq [1].

netlist: /home/Lab333a/Desktop/NCX_problem_x64/ncx_ERFF/sim_dir/lib/erff_slow_ncx/ERFF/mCK_CK_0000f/mCK_CK_0000f.sp
No .acq file detected
Error: Simulating netlist [/home/Lab333a/Desktop/NCX_problem_x64/ncx_ERFF/sim_dir/lib/erff_slow_ncx/ERFF/mCK_CK_0000f/mCK_CK_0000f.sp] fails for cell ERFF. (NCXFL-5)
Warning: Recheck /home/Lab333a/Desktop/NCX_problem_x64/ncx_ERFF/sim_dir/lib/erff_slow_ncx/ERFF/mCK_CK_0000r/mCK_CK_0000r.acq [1].

loveheihei · 发表于 2013-9-2 17:48:58

回复 3# cheming0947

如果你是用的腳本語言來控制的話，建議檢查下腳本某些語句的正確性。我之前的問題主要來源於從pdf file上面copy下來的程式存在錯誤，導致了很多變量不能正確的設置導致的。

cheming0947 · 发表于 2013-9-4 15:41:24

謝謝你的回覆，但我之前有使用原有的library檔去轉出cell template及library template，然後再直接利用轉出來的cell template/ library template，要轉回library就會出現相同的問題，而以下是我一些使用的config檔及轉出來的cell template，DFFSR是我用來測試的cell。

-----------config for generate template--------------------------
set model_file cmn90g_3d3_lk_v2d0.l

set netlist_suffix .sp
set template_suffix .opt
set simulator_type hspice
set simulator_exec /usr/cad/synopsys/hspice/cur/hspice/bin/hspice64
set input_library library/slow.lib

set netlist_dir       ./netlists
set simulation_dir    ./sim_dir_template
set work_dir          ./my_work_template

#True for produce template files, False for produce real delay model
set templates true
set timing_arcs_to_template true
set sensitization_to_template true

set timing    false

set farm_type nofarm
set driver_waveform_to_library false
set log_file template.log
set test_simulator false

------------config for regenerate lib--------------------
set model_file cmn90g_3d3_lk_v2d0.l
set netlist_dir ./netlists
set netlist_suffix .sp
set template_suffix .opt
#set simulator_type hspice
set simulator_exec /usr/cad/synopsys/hspice/cur/hspice/bin/hspice64
set output_library erff_slow_ncx.lib

set input_template_dir ./template
set simulation_dir    ./sim_dir
set work_dir          ./my_work

set farm_type nofarm

#True for produce template files, False for produce real delay model
set templates false

#enable AutuFunction
#set auto_function true

#some additional setting
#set hspice_server true

set timing    true
set power       true
#set nldm       true
#set nlpm       true
set constraint true
set design_rules true
#set ccs_timing true
#set ccs_power true

set driver_waveform_to_library false
set log_file erff_slow.log
set test_simulator false
set max_jobs 1

------------DFFSR.opt----------------
* Generated by Liberty NCX vH-2013.03
cell_footprint : dffsr ;
area : 20.4624000 ;
cell_leakage_power : 63841.8600000 ;
ncx_ff : true ;
ncx_create_arcs : D D internal_power states default ;
ncx_create_arcs : CK CK internal_power states D\
  !D ;
ncx_create_arcs : SN SN internal_power states default ;
ncx_create_arcs : RN RN internal_power states default ;
ncx_create_arcs : * * leakage_power states "!D & !CK & SN & RN & !Q & QN"\
  "!D & !CK & SN & RN & Q & !QN"\
  "!D & !CK & SN & !RN & !Q & QN"\
  "!D & !CK & !SN & RN & Q & !QN"\
  "!D & !CK & !SN & !RN & Q & !QN"\
  "!D & CK & SN & RN & !Q & QN"\
  "!D & CK & SN & RN & Q & !QN"\
  "!D & CK & SN & !RN & !Q & QN"\
  "!D & CK & !SN & RN & Q & !QN"\
  "!D & CK & !SN & !RN & Q & !QN"\
  "D & !CK & SN & RN & !Q & QN"\
  "D & !CK & SN & RN & Q & !QN"\
  "D & !CK & SN & !RN & !Q & QN"\
  "D & !CK & !SN & RN & Q & !QN"\
  "D & !CK & !SN & !RN & Q & !QN"\
  "D & CK & SN & RN & !Q & QN"\
  "D & CK & SN & RN & Q & !QN"\
  "D & CK & SN & !RN & !Q & QN"\
  "D & CK & !SN & RN & Q & !QN"\
  "D & CK & !SN & !RN & Q & !QN" ;
ff "IQ" "IQN" {
  clocked_on : CK ;
  next_state : D ;
  clear : !RN ;
  preset : !SN ;
  clear_preset_var1 : H ;
  clear_preset_var2 : L ;
}
pin D {
  direction : input ;
  ncx_internal_power_rise_input_transition_time_index : 0 ;
  ncx_internal_power_fall_input_transition_time_index : 0 ;
  timing {
*** arc id: D_CK_0000
related_pin : CK ;
timing_type : setup_rising ;
ncx_setup_rising_rise_constrained_pin_transition_index : 0 ;
ncx_setup_rising_fall_constrained_pin_transition_index : 0 ;
ncx_setup_rising_rise_related_pin_transition_index : 0 ;
ncx_setup_rising_fall_related_pin_transition_index : 0 ;
  }
  timing {
*** arc id: D_CK_0001
related_pin : CK ;
timing_type : hold_rising ;
ncx_hold_rising_rise_constrained_pin_transition_index : 0 ;
ncx_hold_rising_fall_constrained_pin_transition_index : 0 ;
ncx_hold_rising_rise_related_pin_transition_index : 0 ;
ncx_hold_rising_fall_related_pin_transition_index : 0 ;
  }
}
pin CK {
  direction : input ;
  clock : true ;
  max_transition : 0.5120000 ;
  min_pulse_width_high : 0.1903990 ;
  min_pulse_width_low : 0.1563230 ;
  ncx_internal_power_rise_input_transition_time_index : 0 ;
  ncx_internal_power_fall_input_transition_time_index : 0 ;
  ncx_active_edge : R ;
  ncx_clock : true ;
}
pin SN {
  direction : input ;
  min_pulse_width_low : 0.1563230 ;
  ncx_internal_power_rise_input_transition_time_index : 0 ;
  ncx_internal_power_fall_input_transition_time_index : 0 ;
  ncx_preset : L ;
  timing {
*** arc id: SN_RN_0000
related_pin : RN ;
timing_type : non_seq_hold_rising ;
define ncx_rise_constraint_scalar : true ;
  }
  timing {
*** arc id: SN_CK_0001
related_pin : CK ;
timing_type : setup_rising ;
ncx_setup_rising_rise_constrained_pin_transition_index : 0 ;
ncx_setup_rising_rise_related_pin_transition_index : 0 ;
  }
  timing {
*** arc id: SN_CK_0002
related_pin : CK ;
timing_type : hold_rising ;
ncx_hold_rising_rise_constrained_pin_transition_index : 0 ;
ncx_hold_rising_rise_related_pin_transition_index : 0 ;
  }
}
pin RN {
  direction : input ;
  min_pulse_width_low : 0.1465870 ;
  ncx_internal_power_rise_input_transition_time_index : 0 ;
  ncx_internal_power_fall_input_transition_time_index : 0 ;
  ncx_clear : L ;
  timing {
*** arc id: RN_SN_0000
related_pin : SN ;
timing_type : non_seq_hold_rising ;
define ncx_rise_constraint_scalar : true ;
  }
  timing {
*** arc id: RN_CK_0001
related_pin : CK ;
timing_type : setup_rising ;
ncx_setup_rising_rise_constrained_pin_transition_index : 0 ;
ncx_setup_rising_rise_related_pin_transition_index : 0 ;
  }
  timing {
*** arc id: RN_CK_0002
related_pin : CK ;
timing_type : hold_rising ;
ncx_hold_rising_rise_constrained_pin_transition_index : 0 ;
ncx_hold_rising_rise_related_pin_transition_index : 0 ;
  }
}
pin Q {
  direction : output ;
  function : IQ ;
  max_capacitance : 0.0547550 ;
  ncx_internal_power_rise_input_transition_time_index : 0 ;
  ncx_internal_power_fall_input_transition_time_index : 0 ;
  ncx_internal_power_rise_total_output_net_capacitance_index : 17 ;
  ncx_internal_power_fall_total_output_net_capacitance_index : 17 ;
  ncx_internal_power_rise_equal_or_opposite_output_net_capacitance_index : 0 ;
  ncx_internal_power_fall_equal_or_opposite_output_net_capacitance_index : 0 ;
  timing {
*** arc id: Q_CK_0000
related_pin : CK ;
timing_type : rising_edge ;
timing_sense : non_unate ;
ncx_rising_edge_rise_input_net_transition_index : 0 ;
ncx_rising_edge_fall_input_net_transition_index : 0 ;
ncx_rising_edge_rise_total_output_net_capacitance_index : 2 ;
ncx_rising_edge_fall_total_output_net_capacitance_index : 2 ;
  }
  timing {
*** arc id: Q_SN_0001
related_pin : SN ;
timing_type : preset ;
timing_sense : negative_unate ;
ncx_preset_rise_input_net_transition_index : 0 ;
ncx_preset_fall_input_net_transition_index : 0 ;
ncx_preset_rise_total_output_net_capacitance_index : 2 ;
ncx_preset_fall_total_output_net_capacitance_index : 2 ;
  }
  timing {
*** arc id: Q_RN_0002
related_pin : RN ;
timing_type : clear ;
timing_sense : positive_unate ;
ncx_clear_fall_input_net_transition_index : 0 ;
ncx_clear_fall_total_output_net_capacitance_index : 2 ;
  }
}
pin QN {
  direction : output ;
  function : IQN ;
  max_capacitance : 0.0547550 ;
  timing {
*** arc id: QN_CK_0000
related_pin : CK ;
timing_type : rising_edge ;
timing_sense : non_unate ;
ncx_rising_edge_rise_input_net_transition_index : 0 ;
ncx_rising_edge_fall_input_net_transition_index : 0 ;
ncx_rising_edge_rise_total_output_net_capacitance_index : 2 ;
ncx_rising_edge_fall_total_output_net_capacitance_index : 2 ;
  }
  timing {
*** arc id: QN_SN_0001
related_pin : SN ;
timing_type : clear ;
timing_sense : positive_unate ;
ncx_clear_rise_input_net_transition_index : 0 ;
ncx_clear_fall_input_net_transition_index : 0 ;
ncx_clear_rise_total_output_net_capacitance_index : 2 ;
ncx_clear_fall_total_output_net_capacitance_index : 2 ;
  }
  timing {
*** arc id: QN_RN_0002
related_pin : RN ;
timing_type : preset ;
timing_sense : negative_unate ;
ncx_preset_rise_input_net_transition_index : 0 ;
ncx_preset_rise_total_output_net_capacitance_index : 2 ;
  }
}
pg_pin VDD {
  voltage_name : VDD ;
  pg_type : primary_power ;
}
pg_pin VSS {
  voltage_name : VSS ;
  pg_type : primary_ground ;
}
sensitization {
  D, CK, SN, RN : Q, QN ;
  110000, 011011, 111110, 1 : r, f ;
  001111, 011011, 1, 111110 : f, r ;
  0, 0, 1010, 0 : r, f ;
  0, 1, 1010, 0 : r, f ;
  1, 0, 1010, 0 : r, f ;
  1, 1, 1010, 0 : r, f ;
  0, 0, 0101, 0 : f, r ;
  0, 1, 0101, 0 : f, r ;
  1, 0, 0101, 0 : f, r ;
  1, 1, 0101, 0 : f, r ;
  1100000, 0110100, 1111110, 1 : r, f ;
  0, 0000001, 0110011, 1100111 : f, r ;
  0, 0, 0110011, 1100110 : f, r ;
  0011100, 0110111, 1, 1111110 : f, r ;
  1, 00001, 10111, 00011 : r, f ;
  1, 0, 10110, 00011 : r, f ;
  0011111, 0110100, 1, 1111110 : f, r ;
  1100011, 0110111, 1111110, 1 : r, f ;
  violation;
  1100000, 0110111, 1111101, 1 : r, f ;
  0011111, 0110111, 1, 1111101 : f, r ;
  0, 0000001, 0110011, 1100111 : f, r ;
  0, 0000011, 0110001, 1100111 : 11, 00 ;
  1, 00001, 10111, 00011 : r, f ;
  1, 00011, 10111, 00001 : 00, 11 ;
  0, 0, 01011, 00001 : f, r ;
  0, 0, 01001, 00011 : 11, 00 ;
  0, 1, 01011, 00001 : f, r ;
  0, 1, 01001, 00011 : 11, 00 ;
  1, 0, 01011, 00001 : f, r ;
  1, 0, 01001, 00011 : 11, 00 ;
  1, 1, 01011, 00001 : f, r ;
  1, 1, 01001, 00011 : 11, 00 ;
  11000011, 01101001, 1, 1 : r, f ;
  110000110, 011010011, 1, 1 : r, f ;
  11000000, 01101000, 11111101, 1 : r, f ;
  0, 00000010, 01100111, 11001111 : f, r ;
  0, 11111101, 01100111, 11001111 : f, r ;
  0, 0, 01100111, 11001101 : f, r ;
  00111000, 01101111, 1, 11111101 : f, r ;
  1, 000010, 101111, 000111 : r, f ;
  1, 111101, 101111, 000111 : r, f ;
  1, 0, 101101, 000111 : r, f ;
  00111100, 01101001, 1, 1 : f, r ;
  001111001, 011010011, 1, 1 : f, r ;
  00111111, 01101000, 1, 11111101 : f, r ;
  11000111, 01101111, 11111101, 1 : r, f ;
}