本帖最后由 朱立平 于 2013-9-4 06:29 编辑
For MSB thermalmeter code current mirror array, if you do not use DEM algorithm. Matching is the important issue & control signal arrvial time should be the same, so your control signal should be register out which use APR tool to balance the clock tree edge.
For MSB thermalmeter code without DEM algorithm, the matchng is more important (unit dac turn on sequence should be centered, keep their average value at center, eliminate the process gradient ) & control signal arrvial timing should be balanced (for DEM & no DEM).
Control signal arrvial time take 2 parts: 1. source signal trigger time. Use register out & APR tool to solve this. 2.wire delay time: keep every control signal wire line with the same length can eliminish this.
Maybe you can usa analog background calibration when your DAC operate.
Or you can use foreground calbration by a high resolution SDM ADC, then calibre MSB dac with smaller calibration DAC array.
For LSB binary code DAC, you should also use thermalmeter code element just connect them as binary connect.
For current DAC layout floor plan,sorry I have no experience. But you shoule consider the DAC matching , dummy DAC should around them. Power supply metal (use high leve metal, ex: top metal) should be wide & use matrix power feed net work (VDD & GND).Control signal delay balance should be consider (with the same length, depend on your dac size, wire delay time approximate to (r*c*l^2)/2) r: resistance of per square, c: capacitance per unit area, l: wire length.
JSSC paper is suggest to read, paper of ADI & Cirrus logic is the best.
Read paper & book is important, but thinking by yourself is more important. |
/2 
eetop公众号
创芯大讲堂
创芯人才网
楼主
发表于 2013-8-30 10:10:23
