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电子书(PDF)Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design
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 Authors:
 
 
 Publication Date: May 7, 2013  Edition: 2013
 
 
 
 
 This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance
 
 
 of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by
 
 
 timing
 
 
 constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing
 
 
 requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design
 
 
 
 
 
    Constraints (SDC), the industry-leading format for specifying constraints.http://www.amazon.com/Constraining-Designs-Synthesis-Timing-Analysis/dp/1461432685/ref=sr_1_1?ie=UTF8&qid=1373728716&sr=8-1&keywords=Constraining+Designs+for+Synthesis+and+Timing+Analysis%3A+A+Practical+Guide+to+Synopsys+Design+Constraints+%28SDC%29 | 
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