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楼主: eefanwei

[招聘] NVIDIA 12年11月最新职位内部推荐(上海/北京/深圳/天津)

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 楼主| 发表于 2012-12-19 14:49:13 | 显示全部楼层
现在这个职位招得很急,大家有兴趣可以试试。 我的邮箱是bradf@nvidia.com, QQ 749851002

Sr. ASIC VerificationEngineer (Clock)

Job Description/Qualifications:

RESPONSIBILITIES:

- ASIC Verification for the most complex GPU clock designat both unit level and chip level.

- Debug and fix SOC level issues

- Maintain/Develop the working environment

- Working closely with various unit teams to solve clockissues.

- Support backend team’s work as the bridge betweenfrontend and backend

MINIMUMREQUIREMENTS:

- Experience in both unit level and chip level verification.

- Good at debugging and problem solving.

- Experience in verification methodology development.

- Programming skills in C and PERL.

- Familiar with clock logic is preferred, such as PLL,clock dividers, trimmers, clock switches, etc.

- Good communication skills, creative, and proactive.

- The ideal candidate will be familiar with all aspectsof the frontend ASIC design flow including RTL design, verification, synthesis,and timing analysis

- BS in Electronic Engineering, MS preferred.

发表于 2012-12-19 20:36:26 | 显示全部楼层
工作地点在深圳么?看你写了好几个地点呢
 楼主| 发表于 2012-12-20 16:13:04 | 显示全部楼层
回复 12# lindan0609


   你是指Sr. ASIC VerificationEngineer (Clock)吗?这个是在上海
 楼主| 发表于 2012-12-24 16:59:49 | 显示全部楼层
芯片设计方面的职位有一些增加,请直接看附件的职位描述 DFT engineer.docx (14.84 KB, 下载次数: 0 )

display Senior ASIC Design Engineer.docx (15.25 KB, 下载次数: 4 )

SoC Verification Engineer.doc (29.5 KB, 下载次数: 2 )

SOC Verification Engineer--Power .docx (14.35 KB, 下载次数: 0 )

Sr ASIC Verification Engineer(Clock).doc (29 KB, 下载次数: 2 )
 楼主| 发表于 2013-2-17 14:13:39 | 显示全部楼层
各位大牛们新年快乐。年后大部分的职位都继续招聘,有兴趣的可以联系我
发表于 2013-2-17 15:44:38 | 显示全部楼层
 楼主| 发表于 2013-2-26 17:35:52 | 显示全部楼层
回复 16# jeffyking


    现在有新的职位出来了,我准备发一个新的帖子,或者你加一下我QQ749851002,我直接发给你
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