cisco最新招聘： Logic Design & Verification Engineer

龚小禅 · 发表于 2008-5-9 17:25:40

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JOB TITLE: ASIC MicroDesign and Verification Engineer

Participate in the design of complex, high-performance, and highly integrated Network Processor chips used in Cisco's networking products. Responsibilities will include micro-architecture and logic design in Verilog. In addition, you will apply your experience in high-speed design timing closure to help partition the design to meet physical design and timing constraints. Work closely with those performing the physical implementation of the design. You will also participate in establishing methodologies for power/clock distribution, timing closure, static timing analysis, power analysis, and generally help to bridge logic design concepts to back-end physical design requirements.

RESPONSIBILITIES

Defining and analyzing architecture and feasibility studies.
Detailed micro-architecture specification, RTL logic design, synthesis and timing closure.
Develop test plans, participate in reference model development and RTL verification and debug.
Participating in reference model development, logic verification, synthesis, formal verification and static timing analysis.

SKILLS AND EXPERIENCE

MSEE/CS combined with 1-3 years of related experience, or BSEE/CS combined with 2-4 years related experience.
Experience in high-performance ASIC design.
Good understanding of ASIC methodologies and flows.
Hands-on experience with HDL (Verilog, SystemVerilog) and tools, scripting and programming languages (Perl, TCL, C++).
Can make design tradeoffs between logical and physical design to optimize for logical requirements, physical complexity, speed, area, power and schedule.
Knowledge in network protocol and experience in switch and router architect.