关于verilog 编译时latches的警告求助

江南炊烟 · 发表于 2012-10-26 16:48:13

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各位我的状态机在状态机转移条件和最终状态机输出上面都引入了key这个变量值，结果编译时警告。代码是这样的：
module key1(key,i,sensor,clk,rst_n,rx_data);
input[3:0] key;//决定触发器被何种信号触发（PC串口，按键，传感器）

input[3:0] sensor;//传感器信号入口
input rst_n;
input[7:0] rx_data;
input clk;
output[3:0] i;

reg[3:0] i;
reg[3:0] freq;
wire[3:0] rx_data_l;
reg[15:0] state,nextstate;
assign  rx_data_l=rx_data[3:0];
//assign  rx_data_l=7;
parameter s0=5'b0,
KEYE=5'b00001,RS485E=5'b00010,
SENSORE=5'b00100,
   FIREB=5'b01000,
   FIRE=5'b10000;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
state<=s0; //复位
else
   state<=nextstate;
end

always @(state or key)
begin
case(state)
s0:if(key==1)nextstate=KEYE;
   else if(key==2)nextstate=RS485E;
else if(key==3)nextstate=SENSORE;
else nextstate=s0; //状态s0
KEYE:if(key==1)
         nextstate=KEYE;
   else if(key==2)
   nextstate=RS485E;
   else if(key==3)
         nextstate=SENSORE;
         else if((key==4)||(key==5)||(key==6)||(key==7))
      nextstate=FIREB;
      else
      nextstate=s0; //状态s4
RS485E:if(key==1)
         nextstate=KEYE;
   else if(key==2)
   nextstate=RS485E;
   else if(key==3)
         nextstate=SENSORE;
   else
   nextstate=s0; //状态s5
SENSORE:if(key==1)
         nextstate=KEYE;
   else if(key==2)
   nextstate=RS485E;
   else if(key==3)
         nextstate=SENSORE;
else
   nextstate=s0; //状态s6
FIREB:if(key==1)
         nextstate=KEYE;
   else if(key==2)
   nextstate=RS485E;
   else if(key==3)
         nextstate=SENSORE;
         else if((key==4)||(key==5)||(key==6)||(key==7))
         nextstate=FIREB;
         else if((key==8)||(key==9))
         nextstate=FIRE;
   else
   nextstate=s0;
FIRE:if(key==1)
         nextstate=KEYE;
   else if(key==2)
   nextstate=RS485E;
   else if(key==3)
         nextstate=SENSORE;
         else if((key==4)||(key==5)||(key==6)||(key==7))
         nextstate=FIREB;
         else if((key==9)||(key==8))
         nextstate=FIRE;
   else
   nextstate=s0;
default:state=s0;
endcase
end

always @(state or key or rst_n)
begin
if(!rst_n) begin
i=4'b0;
end
else begin
/* if (state == KEYE)
      i=key-4'b0011;*/
   if (state == RS485E)
      i=rx_data_l;
   else if (state == SENSORE)
   i=sensor[3:0];
   else if (state == FIREB)
      freq=key;
   else if (state == FIRE)
   i=freq;
   else begin
      i=4'b0000;
   end
end
end

endmodule

警告如下：Warning (10240): Verilog HDL Always Construct warning at key.v(91): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at key.v(91): inferring latch(es) for variable "freq", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at keyinput.v(144): inferring latch(es) for variable "key", which holds its previous value in one or more paths through the always construct
Warning: Node: key1:key1|state.FIREB was determined to be a clock but was found without an associated clock assignment.
跪求大神指点迷津。