做过sigma delta ADC进来下！！！！！！

askermm

自己做实验发现，电路模拟出来的噪底不够低为什么？？？ 从形状来开也达到了5阶整形的效果，但是电路级仿真出来做的图还是不令人满意！！

做为模型，右为电路

hezudao

Opamp gain  gbw

steve_guo_1997

Check your simulation accuracy, not sure what sort tool u were using.

gliang1986

CT or DT?
check the poles and zeros

askermm

回复 3# steve_guo_1997


   SPECTRE

steve_guo_1997

回复 5# askermm

if u were using tran simulation to verify its SNR, this means no actual device noise source was introduced in the final results.
so, there was only several factors that may have influence on your simulation aside from device noise, like
quantization noise (leakage in your loop filter, intermodulation due to  non-linearity , due to modulation if any chopper exists ...)
another possible source is tran algorithm noise introduced by simulator.

I am not sure about your simulation setup or your modulator structure.
if my remember is right, i changed the tolerance setup a lit bit higher than just set the tran simulation accuracy into "conservative " and i should say this was the setup i used in a 16bit SNR SD modulator. Nevertheless, this setup is something relevant to the ckt and may not be suitable for your ckt.
my suggestion is to set the accuracy one step higher than before until the SNR reach stable. Finally, u would get the optimized simulator setup.

hsh22

回复 6# steve_guo_1997


    这仿真速度实在是要命啊

steve_guo_1997

回复 7# hsh22

You almost have no choice. you may choose a  spectre version with multi processor support and hspice may be a better alternative.

askermm

回复 4# gliang1986


   DT.  it is not easy to check in circuit!!!

askermm

回复 6# steve_guo_1997


   have you looked my picture carefully? you can see only three points in my first fig, but more than points in my second fig. why? BTW, i also use "conservative" in my simulator.