在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 7505|回复: 34

Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency

[复制链接]
发表于 2012-5-9 11:01:19 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core. The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems.

Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency.pdf

5.56 MB, 下载次数: 326 , 下载积分: 资产 -3 信元, 下载支出 3 信元

发表于 2012-5-9 20:44:01 | 显示全部楼层
thanks
发表于 2012-5-10 13:40:15 | 显示全部楼层
post before
发表于 2012-5-12 21:34:14 | 显示全部楼层
很不错的书,不过有些年头了,以前就有上传。
发表于 2012-6-5 22:34:09 | 显示全部楼层
Thanks!
发表于 2012-6-22 00:21:16 | 显示全部楼层
资料难得,好好学习
发表于 2012-7-22 16:56:40 | 显示全部楼层
xiexie!!!开始xiangmai书的
发表于 2012-7-31 18:57:52 | 显示全部楼层
看看啊
发表于 2012-8-5 10:36:36 | 显示全部楼层
thanks 多谢了!
发表于 2012-8-6 07:21:32 | 显示全部楼层
great book
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条

×

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-12-23 02:44 , Processed in 0.029386 second(s), 10 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表