请教，v2lvs一般要用到哪些参数？？

zczc999

小弟在做lvs的时候，从verilog转成spice时，不知道用哪些参数合适，只用了-l -s，其他的一般还会用到哪些啊，感觉calibre的manual说的比较难懂。

zhqi415758192

-s0 VSS
-s1 VDD

-v -o

estyzq

回复 2# zhqi415758192


  一般使用v2lvs -v -o -s -s1 -s0

rfid_sh

回复 3# estyzq


    请问您一下，这分别代表什么意思吗？（我是新手，很多不懂，谢谢您了！）

estyzq

回复 4# rfid_sh


   这是别人的帖子的内容，应该说，很详细了，但是常用的只有-s -v -o -s0 -s1

v2lvs -v verilog_design_file -o output_spice_file
[-l verilog_lib_file] [-lsp spice_library_file]
[-lsr spice_library_file] [-s spice_library_file]
[-s0 groundnet] [-s1 powernet] [-sk]
[-p prefix] [-w warning_level]
[-a array_delimiters] [-c char1[char2]]
[-u unnamed_pin_prefix] [-t svdb_dir] [-addpin pin_name]
[-b] [-n] [-i] [-e] [-h]
[-cb][-ictrace]


Arguments
· -v verilog_design_file
Specifies the filename of the input Verilog structural netlist.
· -o output_spice_file
Specifies where to place the output LVS SPICE netlist. Default is standard out.
· -l verilog_lib_file
Specifies the location of the Verilog primitive library file. It is not translated.
· -lsp spice_library_file
Specifies SPICE library file name using pin mode. The SPICE file is parsed for
interface configurations. Pins with pin select ([ ]) annotation are kept as
individual pins using escaped identifiers.
· -lsr spice_library_file
Specifies SPICE library file name using range mode. The SPICE file is parsed
for interface configurations. Pins with pin select ([ ]) annotation are assembled
into Verilog ranges.
· -s spice_library_file
Specifies that the -o output file have a .INCLUDE statement placed at the
beginning that points to the SPICE library file.


· -s0 groundnet
Specifies the default net name for mapping to pin connections with a value of
zero (0). Outputs the specified names in place of Verilog supply0 nets and
generates .GLOBAL declarations in the output netlist.
· -s1 powernet
Specifies the default net name for mapping to pin connections with a value of
one (1). Outputs the specified names in place of Verilog supply1 nets and
generates .GLOBAL declarations in the output netlist.
· -sk
Specifies that Verilog supply0 and supply1 nets are not connected to the global
power and ground nets.
· -p prefix
Adds prefix to Verilog gate level primitive cells.
· -w warning_level
Controls the amount of warning message output. Possible level choices are:
0 Selects to output no warning messages.
1 Selects to output warning messages for skipped blocks and modules only.
2 Selects to output level 1 and calls to undeclared modules and pin arrays
with widths wider than ports. This is the default.
3 Selects to output level 2 and called port array mismatches and
unsupported compiler directives.
4 Selects output level 3 plus all ignored constructs.
· -a array_delimiters
Changes the array delimiter characters. The default is [ ].
· -c char1[char2]
Sets the substitution characters for escaped identifier characters illegal in
SPICE. char1 replaces $, comma, (, ), and =. char2 replaces /. No space is
needed between the two user-supplied arguments.


· -u unnamed_pin_prefix
Specifies a prefix to add to unnamed pin connections in module instantiations.
· -t svdb_dir
Adds source netlist pin direction information to the SVDB. This is used in
Calibre xRC.
· -addpin pin_name




问前可先google一下

rfid_sh

回复 5# estyzq


    谢谢了！

damonzhao

http://bbs.eetop.cn/thread-319075-1-1.html

yxxjtu

等下楼主，如果翻译成终中文就更好了！

永不言弃

路过 学习一下

dennisi123

我用的命令如下：
v2lvs -v top_order1_pg.v -o top_order1_pg.cdl -s /home/LHG/zhangzy/2004/2004.12/csm35/v1.0/spice/typ/CSM35OS142.spc  -s0 VSS -s1 VDD

虽然导出文件成功了，但是提示有warining，请问这些warning会影响lvs吗？我没有找到Verilog primitive library file。
Warning: No module declaration for module dfcrq2 first encountered in module shiftreg
0123
Warning: Duplicate instance name "U1" found in module "shift_inputreg" while doing ca
se-insensitive lookup