Low Phase Noise, High Bandwidth Frequency Synthesis Techniques

hi_china59

Low Phase Noise, High Bandwidth Frequency Synthesis Techniques
by
Scott Edward Meninger
Submitted to the Department of Electrical Engineering and Computer
Science in partial fulfillment of the requirements for the degree of
Doctor of Philosophy at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY
May 2005

Contents
1 Area of Focus: Fractional-N Synthesis 29
1.1 The Issue of Fractional-NQuantization Noise . . . . . . . . . . . . . 30
1.2 Prior Work Aimed at Reducing Fractional-N Quantization Noise . . . 31
1.3 Proposed Quantization Noise Reduction Technique . . . . . . . . . . 33
1.4 Thesis Scope and Contributions . . . . . . . . . . . . . . . . . . . . . 35
1.4.1 System Analytical NoiseModeling . . . . . . . . . . . . . . . . 36
1.4.2 BehavioralModeling and Simulation . . . . . . . . . . . . . . 37
1.4.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.4.4 Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.4.5 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2 Frequency Synthesis Background 45
2.1 Motivation for Fractional-N Synthesis . . . . . . . . . . . . . . . . . . 45
2.1.1 Mixer-based Transceivers . . . . . . . . . . . . . . . . . . . . . 45
2.1.2 DirectModulation Transmission . . . . . . . . . . . . . . . . . 47
2.2 Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2.1 Integer-N Synthesis . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2.2 Fractional-N Synthesis . . . . . . . . . . . . . . . . . . . . . . 49
2.2.3 Phase Interpolation Based Fractional-N Synthesis . . . . . . . 52
2.2.4 ΣΔFractional-N Synthesis . . . . . . . . . . . . . . . . . . . . 54
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3 Fractional-N Synthesizer Noise Modeling 57
3.1 Basics of NoiseModeling of Fractional-N Synthesizers . . . . . . . . . 57
3.2 A New AnalyticalModel View of Fractional-N Synthesizers . . . . . . 60
3.2.1 Phase Interpolation Fractional-N Synthesis . . . . . . . . . . . 61
3.2.2 ΣΔFractional-N Synthesis . . . . . . . . . . . . . . . . . . . . 70
3.2.3 Similarity Between a Fractional-N Synthesizer and ΣΔ MASH
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4 Proposed Quantization Noise Reduction Technique 75
4.1 The PFD/DAC Approach . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.1 The PFD/DAC Approach: Constant Charge Delivery . . . . . 78
4.1.2 Comparison of Charge Balance in a Classical Fractional-N Synthesizer
with the PFD/DAC Synthesizer . . . . . . . . . . . . 82
4.1.3 An Alternative Explanation of the PFD/DAC Approach . . . 84
4.1.4 Model for the PFD/DAC Synthesizer . . . . . . . . . . . . . . 89
4.1.5 The Issue ofMismatch . . . . . . . . . . . . . . . . . . . . . . 90
4.2 Proposed Solution: A Mismatch Compensated PFD/DAC Synthesizer
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2.1 Using a Noise Shaped Cancellation DAC for Improved In-band
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.2 Non-idealitiesWithin the Charge-box . . . . . . . . . . . . . . 95
4.2.3 PFD/DAC Unit Element Mismatch and Compensation . . . . 96
4.2.4 PFD/DAC Internal Timing Mismatch and Compensation . . . 97
4.2.5 Shape Mismatch Between the Error Signal and Cancellation
Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5 Behavioral Simulation of Fractional-N Synthesizers 105
5.1 Setting the PLL Dynamics and Preliminary Noise Analysis Using the
PLL Design Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.2 PFD/DAC Synthesizer Base BehavioralModel . . . . . . . . . . . . . 109
5.2.1 Loop Filter and Loop Gain Calculation . . . . . . . . . . . . . 111
5.2.2 Baseline Noise Calculations . . . . . . . . . . . . . . . . . . . 112
5.2.3 Detector Phase Noise Calculation . . . . . . . . . . . . . . . . 113
5.2.4 VCO Phase Noise Calculation . . . . . . . . . . . . . . . . . . 115
5.2.5 Baseline Phase Noise Simulation . . . . . . . . . . . . . . . . . 118
5.2.6 Baseline Dynamic Performance . . . . . . . . . . . . . . . . . 119
5.3 Behavioral Simulation of Non-Idealities and Proposed Compensation
Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3.1 Compensation of Magnitude Mismatch in the Charge-Box . . 121
5.3.2 Source of Unit Element Mismatch . . . . . . . . . . . . . . . . 124
5.3.3 Compensation of TimingMismatch in the Charge Box . . . . 125
5.3.4 Eliminating ShapeMismatchWith a Sample-and-Hold . . . . 127
5.3.5 A Digital Compensation Scheme for Reducing Shape Mismatch
Spurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.6 Impact of Finite PFD/DAC Settling . . . . . . . . . . . . . . 132
5.3.7 Impact of Finite Charge-Pump Output Impedance . . . . . . . 134
5.3.8 Impact of Unity Gain Buffer Non-linearity . . . . . . . . . . . 137
5.4 Choosing the PFD Architecture for Best Charge-Pump Linearity . . . 141
5.4.1 Classic Tri-state PFD. . . . . . . . . . . . . . . . . . . . . . . 141
5.4.2 Overlapping Tri-state PFD . . . . . . . . . . . . . . . . . . . . 144
5.4.3 Offset Tri-state PFD . . . . . . . . . . . . . . . . . . . . . . . 146
5.4.4 Overlapping and Offset PFD . . . . . . . . . . . . . . . . . . . 148
5.5 GMSKModulated Synthesizer Model . . . . . . . . . . . . . . . . . . 149
5.5.1 Direct GMSKModulation . . . . . . . . . . . . . . . . . . . . 149
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6 Circuit Design 155
6.1 Divider and Divider Retimer . . . . . . . . . . . . . . . . . . . . . . . 156
6.1.1 High-speed,Multi-modulus Divider . . . . . . . . . . . . . . . 157
6.1.2 Retiming and the Issue of Meta-stability . . . . . . . . . . . . 157
6.1.3 Divider Retimer . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.1.4 A Phase-space Methodology for Understanding Divider Retiming160
6.1.5 Divider Retimer Operation In Phase-space . . . . . . . . . . . 162
6.2 PFD Logic and Timing Compensation . . . . . . . . . . . . . . . . . 165
6.3 PFD/DAC Unit Element Current Source . . . . . . . . . . . . . . . . 167
6.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.5 Unity Gain Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . 173
6.6 Op-amp and Buffer Noise Considerations . . . . . . . . . . . . . . . . 175
6.7 Sample and Hold Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 176
6.7.1 Charge Injection and Compensation . . . . . . . . . . . . . . . 178
6.7.2 Differential-to-single-ended Converter . . . . . . . . . . . . . . 181
6.8 High Speed I/O Design . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.8.1 VCO and Reference Input Buffer . . . . . . . . . . . . . . . . 183
6.8.2 Output Band Select Divider . . . . . . . . . . . . . . . . . . . 184
6.9 Prototype PFD/DAC Synthesizer IC . . . . . . . . . . . . . . . . . . 186
6.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7 Measured Results 187
7.1 Prototype Mismatch Compensated PFD/DAC Synthesizer System . . 188
7.1.1 System Programmability . . . . . . . . . . . . . . . . . . . . . 188
7.2 BaselineMeasured Performance: The Integer-N Synthesizer . . . . . . 190
7.2.1 Reference Buffer Jitter Induced Noise . . . . . . . . . . . . . . 193
7.2.2 PFD Reset Jitter Induced Noise . . . . . . . . . . . . . . . . . 195
7.2.3 Reference Jitter Extraction Using the AnalyticalModel . . . . 198
7.3 Un-Modulated PFD/DAC Synthesizer Measured Performance . . . . 200
7.3.1 PFD/DAC Synthesizer Vs. Integer-N Synthesizer . . . . . . . 200
7.3.2 PFD/DAC Timing Mismatch Extraction Using the Analytical
Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.3.3 Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . 203
7.3.4 PFD/DAC Synthesizer Vs. ΣΔSynthesizer . . . . . . . . . . 204
7.3.5 Impact of Sample-and-Hold Loop Filter and Spurious Performance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3.6 Comparison to PriorWork . . . . . . . . . . . . . . . . . . . . 208
7.4 Modulated Synthesizer Measured Performance . . . . . . . . . . . . . 213
7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8 Conclusions and Future Work 219
8.1 Mismatch Compensated PFD/DAC Synthesizer . . . . . . . . . . . . 219
8.2 AnalyticalModeling Contributions . . . . . . . . . . . . . . . . . . . 220
8.3 BehavioralModeling Contributions . . . . . . . . . . . . . . . . . . . 220
8.4 Circuit Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.5 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.5.1 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . 222
8.5.2 Intrinsic Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
A Chip Pinout and Bonding Diagram 225
B Synthesizer Configuration Register 229
B.1 Register Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
B.2 General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 232
B.3 Bias Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
B.4 Divider Retimer Configuration . . . . . . . . . . . . . . . . . . . . . . 236
B.5 S/H Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
B.6 PFD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

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