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发表于 2011-5-26 13:27:34
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Wire Load Models
For timing analysis performed before placement and routing, Design Compiler must estimate the wire delays. The simplest estimation method is the wire load model, which gets a rough value for the total wire capacitance, based on the size of the chip and the fanout of the net. Larger chip sizes and larger fanouts are assumed to result in longer wires and more resistance and capacitance. Wire load models are not used in IC Compiler because accurate wire information is available from the layout database.
For logic synthesis, you should use Design Compiler with topographical technology, if available, because it produces better results than wire load models. However, if you are not using Design Compiler in topographical mode, you can use wire load models to estimate the capacitance, resistance, and area of nets before floorplanning or layout. The wire load models provided in the technology library define the fanout-to-length relationships.
Note:
Wire load models are used only with Design Compiler running in standard mode, not topographical mode. Design Compiler with topographical technology and IC Compiler have better wire estimation methods, so wire load models are not used with these tools.
With wire load models, Design Compiler estimates the wire lengths of pin-to-pin connections based on fanout count, and then uses those estimates to calculate the effects of cell placement and wire routing. Fanout is the total number of pins on the net, excluding the driver pin.
The wire load model is defined in the library specification. In Liberty library syntax, the wire_load group defines the wire loads. For more information, see the Library Compiler documentation.
Design Compiler determines which wire load model to use for a design according to the wire load model you define with the set_wire_load_model command, the wire load indicated by the technology library’s wire_load_selection group, or the wire load model identified by the default_wire_load attribute in the library, in that order. If none of these items are defined, no wire load model is used. and the net resistance, capacitance, and delay values are zero.
Net Capacitance, Resistance, and Area Calculation
To calculate the capacitance of a net, Design Compiler performs the following steps:
1.
Determines the fanout of the net.
2.
Looks up the length in the wire load model.
3.
Calculates the capacitance by multiplying the length by the capacitance coefficient in the wire load model.
Example
Suppose that a wire load model is defined as follows in the library:
wire_load("90x90") {
capacitance : 2.0 ; /* C per unit-length */
resistance :100.0 ; /* R per unit-length */
area : 0.5 ; /* net-area per unit-length */
slope : 1.5 ; /* extrapolation slope */
fanout_length(1,1) ; /* fanout_length pairs */
fanout_length(2,2.2);
fanout_length(3,3.3);
fanout_length(4,4.4);
}
To determine lumped net capacitance, total net resistance, and the design area due to the net, Design Compiler multiplies the capacitance, resistance, and area scaling factors by the estimated wire length.
Design Compiler calculates the net fanout value as the total number of pins on the net excluding one driver pin. For example, on a net with 2 fanin pins and 3 fanout pins, the fanout value is
(2 + 3) - 1 = 4
It calculates the lumped net capacitance by multiplying of the estimated wire length by the capacitance factor 2.0. For a fanout value of 4, the last fanout_length defines the wire length as 4.4, resulting in a calculated lumped net capacitance of
2.0 * 4.4 = 8.8
It calculates the total net resistance by multiplying the estimated wire length by the resistance factor, yielding a value of
4.4 * 100.0 = 440.0
When calculating pin-to-pin RC delays, Design Compiler interprets the total net resistance on the basis of the current operating condition’s tree_type attribute.
Design Compiler calculates the net area by multiplying the estimated wire length by the area factor, yielding a value of
4.4 * .5 = 2.2
Design Compiler uses the net area to measure the impact of different optimization possibilities on the total design area of the chip. An accurate net area estimate guides Design Compiler in selecting the best optimization for minimizing area.
Design Compiler uses interpolation between and extrapolation beyond the library-defined wire load values.
其实我一直没有好好琢磨过WLM的概念，跟如何去计算 R & C。 |
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发表于 2011-5-26 08:50:52
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