Signal Integrity Simulation of PCI Express Gen 2 Channel[Paper]

drjiachen

Overview
In the electronics industry, there has been an architectural shift over the past
several years from parallel bus interfaces to serial communication links. The benefits
of employing serial links over parallel I/O schemes include fewer device pins,
reduced board space requirements, smaller connectors, easier PCB layouts, and less
susceptibility to noise. However, there are unique challenges associated with serial
link design. The high data rate signals pose challenges previously only familiar to
analog RF and microwave designers. Today, many existing serial I/O standards operate
at multi-Gbps speeds. These standards are evolving, and the next generation
versions of the standards aim to increase (or perhaps even double) the data rates
achievable in a single lane. For example, PCI Express (PCIe) Gen 1 operates at 2.5
GT/s, while PCIe Gen 2 and PCIe Gen 3 are 5.0 GT/s and 8.0 GT/s, respectively. Further
complicating things is the fact that high-speed serial links often require special
data processing, such as SerDes (serializer/deserializer), equalization, and line coding
(i.e. 8B10B or 64B66B). For multi-Gbps serial links, a robust approach to signal
integrity simulation must be followed in order to avoid costly design iterations.
Signal Integrity Simulation of PCI Express Gen 2 Channel.pdf (1.82 MB , 下载次数: 221 )

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aouqpncxwiju

非常感谢

scorpion

thanks a lot

paddywcw

Thanks a lot

apteye

thanks

wjh123

Thanks you.

wjh123

Thanks

maxlover

回复 1# drjiachen


   GOOD article

maxlover

回复 1# drjiachen


   Thanks

guofu2010

回复 1# drjiachen


    非常感谢