有没有用Questa10.0a跑UVM 1.0成功的？

cnzhang

我按照网上的做法，老是不成功，抑郁了。麻烦告诉指点一下哈！
set UVM_HOME D:/study/uvm/questasim-win32-10.0a/verilog_src/uvm-1.0/src
vlog +incdir+$UVM_HOME/src hello_world.sv
# QuestaSim vlog 10.0a Compiler 2011.02 Feb 20 2011
# -- Compiling module hello_world
# -- Importing package uvm_pkg
# ** Error: packet.sv(29): (vlog-2163) Macro `uvm_object_utils_begin is undefined.
# ** Error: packet.sv(29): near "(": syntax error, unexpected '(', expecting function or task
# ** Error: packet.sv(30): (vlog-2163) Macro `uvm_field_int is undefined.
# ** Error: packet.sv(31): (vlog-2163) Macro `uvm_object_utils_end is undefined.
# ** Error: producer.sv(24): Undefined variable: T.
# ** Error: producer.sv(32): near "protected": syntax error, unexpected protected
# ** Error: producer.sv(36): (vlog-2163) Macro `uvm_component_utils_begin is undefined.
# ** Error: producer.sv(37): (vlog-2163) Macro `uvm_field_object is undefined.
# ** Error: producer.sv(38): (vlog-2163) Macro `uvm_field_int is undefined.
# ** Error: producer.sv(39): (vlog-2163) Macro `uvm_field_int is undefined.
# ** Error: producer.sv(40): (vlog-2163) Macro `uvm_component_utils_end is undefined.
# ** Error: producer.sv(46): (vlog-2163) Macro `uvm_info is undefined.
# ** Error: producer.sv(46): near "(": syntax error, unexpected '('
# ** Error: producer.sv(52): near "(": syntax error, unexpected '(', expecting IDENTIFIER or TYPE_IDENTIFIER
# ** Error: producer.sv(53): near "(": syntax error, unexpected '(', expecting IDENTIFIER or TYPE_IDENTIFIER
# ** Error: producer.sv(55): near "(": syntax error, unexpected '(', expecting IDENTIFIER or TYPE_IDENTIFIER
# ** Error: producer.sv(58): near ".": syntax error, unexpected '.', expecting IDENTIFIER or TYPE_IDENTIFIER or '#' or '('
# ** Error: producer.sv(62): (vlog-2163) Macro `uvm_info is undefined.
# ** Error: producer.sv(67): near "(": syntax error, unexpected '(', expecting IDENTIFIER or TYPE_IDENTIFIER
# ** Error: producer.sv(73): (vlog-2163) Macro `uvm_info is undefined.
# ** Error: consumer.sv(24): near "#": syntax error, unexpected '#', expecting ')' or ','
# ** Error: consumer.sv(25): 'out' already declared in this scope (packet).
# ** Error: consumer.sv(27): Multiple constructors declared for class packet - only one allowed.
# ** Error: consumer.sv(27): 'name' already declared in this scope (new).
# ** Error: consumer.sv(27): Verilog Compiler exiting
# D:/study/uvm/questasim-win32-10.0a/win32/vlog failed.

whxqq

找不到宏呢，兄弟Questa10.0a哪下的啊?

gaurson

我编译的时候，除了你上面的指令，我在编译hello_world.sv之前，把uvm_pkg给编译了一遍，就可以了。

cnzhang

回复 3# gaurson
谢谢哈！我下去试试

cnzhang

回复 2# whxqq

就在官网上面，注册就可以了。
eetop里面有下载的教程，不过链接我忘记了。。。
你可以找找看

cnzhang

回复 1# cnzhang
搞定了，sign。。。
vlog -timescale "1ns/1ns" -mfcu -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+$UVM_HOME $UVM_HOME/uvm.sv +incdir+. hello_world.sv
不过具体没有命令是什么意思还是要研究研究。

fpga2008dut

uvm的例子里面有questa脚本，这个在modelsim6.5c中也是可以运行的，可能questa支持uvm更好些，不知道大侠的questa10.0a是在哪里下载的

sssshust1

先下下来试试啦

superpig2b

一会试一试

nishuidegou

顶一下