分享2个职位，30万左右年薪：PR 以及 PV

idbi

第一个：
Staff Physical Design Engineer 2
Responsibilities:

Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Define and evolve backend low-power design methodology in 40nm technology to support aggressive low-power techniques for chips having multiple power-domains and dynamic voltage-scaling.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Integrate of analog and RF-macros using their library models and closing timing at the interface level.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule,resource requirements and track backend schedule.

Qualifications:

Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.
Proven track records of leading multiple product tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.
Vast experience identifying and resolving physical implementation issues related to Congestion, Routing & Timing Closure (including Crosstalk)
Hands on experience and detailed knowledge of Synopsys (preferred), Cadence or Magma Physical Design-tools.
Expertise in scripting languages like PERL, TCL, AWK, shell, etc. Must be a team player with excellent verbal and written communication skill.
8+ years of direct experience on physical design (MS 6+ years)

第二个：
Staff Physical Verification Engineer   1
Responsibilities:
Assist multiple XX design groups in physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout reviews, as well as maintaining physical verification flow, layout and add-on tools. You also will take physical design (P&R) projects from time to time.

Qualifications:
Expert user of Cadence Virtusso, Laker or Mentor IC-Station.
Expert user of Mentor*s Calibre or Synopsys* Hercules runsets or ruledecks creation and debugging.
Must be programming-minded capable of writing Tcl or Perl.
In-depth understanding of fabrication processing steps used in major foundries.
Proven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results.
Self-motivated team worker, good verbal and written communication skills.
Knowledge of Synopsys Place-and-Route tools
Must able to work under tapeout pressure and tight schedule
8+ years of direct experience on IC layout, physical verification and tapeout (MS 6+years)

paulszicc

good position，so good ,but i can not.

idbi

没关系，还有很多其他层次的职位。
有兴趣的给我发email：YestinAi@gmail.com

paulszicc

谢谢，将来有机会再说了。

mrandlf

对刚刚进公司学习pr的我，这要求也太高了

hzg51

这是咱的奋斗目标呀！

flytearing1978

表示羡慕的说！

ohgreat

要求也太高了！

zsyz

可望不可即啊

paulszicc

只是要求而已，真正符合的，应该已是group mgr或至少年薪不少于30万了。这个级别的人，不会为了小于5万的增长而跳槽的。 所以，难啊