Wireless CMOS Frequency Synthesizer Design

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Wireless CMOS Frequency Synthesizer Design

http://www.amazon.com/Wireless-Frequency-Synthesizer-International-Engineering/dp/1441950346/ref=sr_1_1?ie=UTF8&s=books&qid=1299418358&sr=1-1

Authors:  J. Craninckx  Michiel Steyaert
Paperback: 280 pages
Publisher: Springer; 1st Edition. edition
Language: English
ISBN-10: 1441950346
ISBN-13: 978-1441950345

1. INTRODUCTION
   1.1 Modern Telecommunications
   1.1.1 A Short History
   1.1.2 Digital Cellular Systems
   1.2 Integrating a Transceiver
   1.3 Frequency Synthesizer Types
   1.3.1 The Table-Look-Up Synthesizer
   1 .3.2 The Direct Synthesizer
   1.3.3 The Phase-Locked Loop Synthesizer
   1.3.4 Combination of Techniques
   1.4 The Presented Work

2. PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS
   2.1 Introduction
   2.2 Definition of Phase Noise
   2.3 PLL Fundamentals
   2.3.1 Noise Characteristics
   2.3.2 Transient Characteristics
   2.3.2.1 Tracking
   2.3.2.2 Acquisition
   2.4 PLL Building Blocks
   2.4.1 Phase Detector
   2.4.1.1 Multipliers
   2.4.1 .2 Exclusive OR Gate
   2.4.1 .3 Flip-Flop
   2.4.1.4 Phase-Frequency Detector
   2.4.2 Loop Filter
   2.4.2.1 First-Order PLL
   2.4.2.2 Second-Order PLL
   2.4.2.4 Charge-Pump PLL 34
   2.4.3 Voltage-Controlled Oscillator 35
   2.4.3.1 Crystal Oscillators 36
   2.4.3.2 Relaxation Oscillators 38
   2.4.3.3 Ring Oscillators 39
   2.4.3.4 LC-Oscillators 40
   2.4.3.5 OTA-C Oscillators 41
   2.4.3.6 Other Configurations 41
   2.4.4 Frequency Divider 41
   2.4.4.1 Programmable Dividers or Counters 42
   2.4.4.2 Prescalers 43
   2.4.4.3 Fractional-N Synthesis 44
   2.5 Conclusion 46

3. VOLTAGE-CONTROLLED OSCILLATOR PHASE NOISE 49
   3.1 Introduction 49
   3.2 Oscillator Theory 50
   3.2.1 Q : the"Quality factor 52
   3.2.2 Active Inductors 53
   3.2.2.1 Circuit implementation 53
   3.2.2.2 Noise in Active Inductors 54
   3.2.3 Passive Inductors 55
   3.3 Phase Noise of a Basic Oscillator with Passive Inductor 57
   3.3.1 Parallel Resistance R" 57
   3.3.2 Inductor Series Resistance R, 59
   3.3.3 Capacitor Series Resistance Rc 60
   3.3.4 Effective Resistance ·61
   3.3.5 Active Element C M 61
   3.3.6 Conclusion 62
   3.4 Phase Noise of a Basic Oscillator with Active Inductor 63
   3.4.1 Inductor Current Noise Source 64
   3.4.2 Inductor Voltage Noise Source 64
   3.4.3 Total Noise 65
   3.4.4 Conclusion 66
   3.4.5 Comparison with Bandpass Filters 67
   3.5 Phase Noise in Crystal Oscillators 68
   3.5.1 Parallel Resistance R" 68
   3.5.2 Other Parasitic Resistors 70
   3.5.3 Effective Resistance and Capacitance 71
   3.5.4 Active Element C M 71
   3.5.5 Noisy Inductor Ls 72
   3.5.6 Case Study: the CMOS Pierce Crystal Oscillator 73
   3.5.7 Conclusion 75
   3.6 Enhanced LC-Tanks 78
   3.7 Other Phase Noise Sources 80
   3.7.1 FM-modulation 81
   3.7.2 Ilf Noise 83
   3.8 State-of-the-Art Integrated VCOs 83
   3.9 Conclusions 87

4. BONDING WIRE INDUCTANCE VCOS 89
   4.1 Introduction 89
   4.2 Bonding Wire Inductors 90
   4.2.1 Inductance Calculation 90
   4.2.2 Bonding Wire Test VCO 93
   4.2.3 Inductance Variation 95
   4.2.4 Parasitics 98
   4.2.4.1 Bonding Pad Parasitics 98
   4.2.4.2 Inductor Series Resistance 103
   4.2.4.3 Substrate Loss 104
   4.2.4.4 Magnetic Coupling 106
   4.3 Enhanced Bonding Wire LC-tank 106
   4.4 Amplifier Design 111
   4.4.1 Circuit Schematic 111
   4.4.2 Bipolar or CMOS? 112
   4.4.3 Circuit Sizing 113
   4.5 Measurement Results 114
   4.6 Conclusions 118

5. PLANAR-INDUCTOR VCOS 121
   5.1 Introduction 121
   5.2 Planar Inductors 122
   5.2.1 First-Order Inductance Calculation 125
   5.2.2 Finite-Element Simulations 126
   5.2.2.1 Metal Losses 128
   5.2.2.2 Substrate Losses 132
   5.2.2.3 Inductor Design Model 134
   5.2.3 Hollow Coil Design Guidelines 135
   5.3 Planar-LC VCO Design on a Heavily Doped Substrate 136
   5.3.1 Coil Geometry 137
   5.3.2 Amplifier Design 139
   5.3.3 Measurement Results, 140
   5.4 Planar-LC VCO Design on a Lowly Doped Substrate 142
   5.4.1 Coil Geometry 144
   5.4.2 Amplifier Design 149
   5.4.3 Measurement Results 151
   5.4.3.1 900-MHz Design 151
   5.4.3.2 1.8-GHz Design 156
   5.5 Conclusions 156

6~--HIGH-FREQUENCY CMOS PRESCALERS 161
   6.1 Introduction 161
   6.2 Phase-Switching Dual-Modulus Prescaler Architecture 162
   6.2.1 Conventional Topology 162
   6.2.2 Phase-Switching Topology 164
   6.2.3 Variations on the Basic Topology 166
   6.3 A Dual-Modulus Divide-by-128/129 Prescalerin 0.7-I.tm CMOS 168
   6.3.1 Circuit Design 168
   6.3.1.1 Full-Frequency Divide-by-2 168
   6.3.1.2 Half-Frequency Divide-by-2 172
   6.3.1.3 Phase-Selection 173
   6.3.1.4 Low-Frequency Divide-by-32 176
   6.3.2 Measurement Results 176
   6.4 An Eight-Modulus Prescaler in O.4-J,lm CMOS 177
   6.4.1 Circuit Design
   6.4.2 Measurements
   6.5 Conclusions

7. A FULLY INTEGRATED CMOS PLL FREQUENCY SYNTHESIZER
   7.1 Introduction
   7.2 Phase-Frequency Detector
   7.3 Loop Filter
   7.3.1 Charge Pump
   7.3.2 Filter Impedance
   7.3.3 Active or Passive Filter?
   7.4 Noise Aspects
   7.4.1 Charge Pump Noise
   7.4.2 Filter Impedance Noise
   7.4.3 4-th Order PLL
   7.5 Improved Loop filter
   7.5.1 Filter topology
   7.5.2 Transfer Functions
   7.5.2.1 Open Loop Gain
   7.5.2.2 Charge Pump Noise
   7.5.2.3 Loop Filter Noise
   7.5.3 Filter Optimization
   7.6 Linearization
   7.7 Measurements
   7.7.1 Phase Noise Performance
   7.7.2 Transient Characteristics
   7.8 Conclusions

8. GENERAL CONCLUSIONS

Bibliography

Index

dannymu

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amplifier_bias

AlexKe

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crazy_py

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qinsi

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alex_2012

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tsod

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cdting

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newrfdesign

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wyfchinaitlab

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