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本帖最后由 yahol 于 2011-3-5 17:18 编辑
ISSCC 2011 Sessions and Articles List [目录下方即下载地址]
Session 1 - Plenary
1.0 - Session 1 Overview: Plenary
1.1 - New Interfaces to the Body Through Implantable System Integration
1.2 - Game-Changing Opportunities for Wireless Personal Healthcare and Lifestyle
1.3 - Eco-Friendly Semiconductor Technologies for Healthy Living
1.4 - Beyond the Horizon: The Next 10x Reduction in Power - Challenges and Solutions
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Session 2 - Technologies For Health
2.0 - Session 2 Overview: Technologies For Health
2.1 - A 0.24nJ/b Wireless Body-Area-Network Transceiver with Scalable Double-FSK Modulation
2.2 - A 75μW Real-Time Scalable Network Controller and a 25μW ExG Sensor IC for Compact Sleep-Monitoring Applications
2.3 - A 3µW Wirelessly Powered CMOS Glucose Sensor for an Active Contact Lens
2.4 - A 90nm CMOS SoC UWB Pulse Radar for Respiratory Rate Monitoring
2.5 - A Broadband THz Imager in a Low-Cost CMOS Technology
2.6 - A Programmable Implantable Micro-Stimulator SoC with Wireless Telemetry: Application in Closed-Loop Endocardial Stimulation for Cardiac Pacemaker
2.7 - A 660pW Multi-Stage Temperature-Compensated Timer for Ultra-Low-Power Wireless Sensor Node Synchronization
2.8 - A Low-Power Fully Integrated RF Locked Loop for Miniature Atomic Clock
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Session 3 - RF Techniques
3.0 - Session 3 Overview: RF Techniques
3.1 - Spur-Free All-Digital PLL in 65nm for Mobile Phones
3.2 - A 5.3GHz Digital-to-Time-Converter-Based Fractional-N All-Digital PLL
3.3 - A 2.5GHz 32nm 0.35mm2 3.5dB NF -5dBm P1dB Fully Differential CMOS Push-Pull LNA with Integrated 34dBm T/R Switch and ESD Protection
3.4 - A 65nm CMOS Pulse-Width-Controlled Driver with 8Vpp Output Voltage for Switch-Mode RF PAs up to 3.6GHz
3.5 - A Low-Power Process-Scalable Superheterodyne Receiver with Integrated High-Q Filters
3.6 - A 40nm CMOS Highly Linear 0.4-to-6GHz Receiver Resilient to 0dBm Out-of-Band Blockers
3.7 - A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution
3.8 - A Harmonic Rejection Mixer Robust to RF Device Mismatches
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Session 4 - Enterprise Processors & Components
4.0 - Session 4 Overview: Enterprise Processors & Components
4.1 - A 5.2GHz Microprocessor Chip for the IBM zEnterpriseTM System
4.2 - Dynamic Hit Logic with Embedded 8Kb SRAM in 45nm SOI for the zEnterpriseTM Processor
4.3 - A 32nm Westmere-EX Xeon® Enterprise Processor
4.4 - Godson-3B: A 1GHz 40W 8-Core 128GFLOPS Processor in 65nm CMOS
4.5 - Design Solutions for the Bulldozer 32nm SOI 2-Core Processor Module in an 8-Core CPU
4.6 - 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core
4.7 - Clock Generation for a 32nm Server Processor with Scalable Cores
4.8 - A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium® Processor for Mission-Critical Servers
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Session 5 - PLLs
5.0 - Session 5 Overview: PLLs
5.1 - A 2.9-to-4.0GHz Fractional-N Digital PLL with Bang-Bang Phase Detector and 560fsrms Integrated Jitter at 4.5mW Power
5.2 - An Injection-Locked Ring PLL with Self-Aligned Injection Window
5.3 - A 0.4-to-3GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Background Calibration
5.4 - A 0.1-fref BW 1GHz Fractional-N PLL with FIR-Embedded Phase-Interpolator-Based Noise Filtering
5.5 - A Scalable sub-1.2mW 300MHz-to-1.5GHz Host-Clock PLL for System-on-Chip in 32nm CMOS
5.6 - A 570fsrms Integrated-Jitter Ring-VCO-Based 1.21GHz PLL with Hybrid Loop
5.7 - A Rotary-Traveling-Wave-Oscillator-Based All-Digital PLL with a 32-Phase Embedded Phase-to-Digital Converter in 65nm CMOS
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Session 6 - Sensors & Energy Harvesting
6.0 - Session 6 Overview: Sensors & Energy Harvesting
6.1 - A Low-Power 3-Axis Digital-Output MEMS Gyroscope with Single Drive and Multiplexed Angular Rate Readout
6.2 - A 50mW CMOS Wind Sensor with ±4% Speed and ±2° Direction Error
6.3 - A Telemetric Stress-Mapping CMOS Chip with 24 FET-Based Stress Sensors for Smart Orthodontic Brackets
6.4 - A 21b ±40mV Range Read-Out IC for Bridge Transducers
6.5 - A ±1.5% Nonlinearity 0.1-to-100A Shunt Current Sensor Based on a 6kV Isolated Micro-Transformer for Electrical Vehicles and Home Automation
6.6 - Indirect X-ray Photon-Counting Image Sensor with 27T Pixel and 15e-rms Accurate Threshold
6.7 - A 1.32pW/frame•pixel 1.2V CMOS Energy-Harvesting and Imaging (EHI) APS Imager
6.8 - 5µW-to-10mW Input Power Range Inductive Boost Converter for Indoor Photovoltaic Energy Harvesting with Integrated Maximum Power Point Tracking Algorithm
6.9 - A Self-Supplied Inertial Piezoelectric Energy Harvester with Power-Management IC
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Session 7 - Multimedia & Mobile
7.0 - Session 7 Overview: Multimedia & Mobile
7.1 - A 216fps 4096 2160p 3DTV Set-Top Box SoC for Free-Viewpoint 3DTV Applications
7.2 - A Highly Parallel and Scalable CABAC Decoder for Next-Generation Video Coding
7.3 - A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer
7.4 - A 57mW Embedded Mixed-Mode Neuro-Fuzzy Accelerator for Intelligent Multi-core Processor
7.5 - A 28nm 0.6V Low-Power DSP for Mobile Applications
7.6 - A MIMO WiMAX SoC in 90nm CMOS for 300km/h Mobility
7.7 - A 70Mb/s -100.5dBm Sensitivity 65nm LP MIMO Chipset for WiMAX Portable Router
7.8 - A Direct Digital Frequency Synthesizer with Minimized Tuning Latency of 12ns
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Session 8 - Architectures & Circuits for Next-Generation Wireline Transceivers
8.0 - Session 8 Overview: Architectures & Circuits for Next-Generation Wireline Transceivers
8.1 - 11.3Gb/s CMOS SONET-Compliant Transceiver for Both RZ and NRZ Applications
8.2 - A Full-Duplex 10GBase-T Transmitter Hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOS
8.3 - A 40Gb/s TX and RX Chip Set in 65nm CMOS
8.4 - 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link
8.5 - A 12.5+12.5Gb/s Full-Duplex Plastic Waveguide Interconnect
8.6 - A Highly Digital 0.5-to-4Gb/s 1.9mW/Gb/s Serial-Link Transceiver Using Current-Recycling in 90nm CMOS
8.7 - A 1-to-6Gb/s Phase-Interpolator-Based Burst-Mode CDR in 65nm CMOS
8.8 - A 14Gb/s High-Swing Thin-Oxide Device SST TX in 45nm CMOS SOI
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Session 9 - Wireless & mm-Wave Connectivity
9.0 - Session 9 Overview: Wireless & mm-Wave Connectivity
9.1 - A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE 802.15.3c
9.2 - A 65nm CMOS Fully Integrated Transceiver Module for 60GHz Wireless HD Applications
9.3 - A 60GHz CMOS Phased-Array Transceiver Pair for Multi-Gb/s Wireless Communications
9.4 - A 65nm CMOS 4-Element Sub-34mW/Element 60GHz Phased-Array Transceiver
9.5 - An 87GHz QPSK Transceiver with Costas-Loop Carrier Recovery in 65nm CMOS
9.6 - A 65nm Dual-Band 3-Stream 802.11n MIMO WLAN SoC
9.7 - A 0.46mm2 4dB-NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS
9.8 - An All-Digital 8-DPSK Polar Transmitter with Second-Order Approximation Scheme and Phase Rotation-Constant Digital PA for Bluetooth EDR in 65nm CMOS
9.9 - A Digital-Intensive Receiver Front-End Using VCO-Based ADC with an Embedded 2nd-Order Anti-Aliasing Sinc Filter in 90nm CMOS
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Session 10 - Nyquist Rate Converters
10.0 - Session 10 Overview: Nyquist Rate Converters
10.1 - A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist
10.2 - A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC
10.3 - An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS
10.4 - A 16b 80MS/s 100mW 77.6dB SNR CMOS Pipeline ADC
10.5 - A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS
10.6 - A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC
10.7 - A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz
10.8 - A 56GS/s 6b DAC in 65nm CMOS with 256 6b memory
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Session 11 - Non-Volatile Memory Solutions
11.0 - Session 11 Overview: Non-Volatile Memory Solutions
11.1 - A 151mm2 64Gb MLC NAND Flash Memory in 24nm CMOS Technology
11.2 - A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability
11.3 - A 32Gb MLC NAND Flash Memory with Vth Margin-Expanding Schemes in 26nm CMOS
11.4 - 95%-Lower-BER 43%-Lower-Power Intelligent Solid-State Drive (SSD) with Asymmetric Coding and Stripe Pattern Elimination Algorithm
11.5 - An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory
11.6 - A Low-Voltage 1Mb FeRAM in 0.13µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin in Scaled CMOS
11.7 - A 4Mb Conductive-Bridge Resistive Memory with 2.3GB/s Read-Throughput and 216MB/s Program-Throughput
11.8 - A 7MB/s 64Gb 3-Bit/Cell DDR NAND Flash Memory in 20nm-Node Technology
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Session 12 - Design in Emerging Technologies
12.0 - Session 12 Overview: Design in Emerging Technologies
12.1 - A 95mV-Startup Step-Up Converter with VTH-Tuned Oscillator by Fixed-Charge Programming and Capacitor Pass-On Scheme
12.2 - 100V AC Power Meter System-on-a-Film (SoF) Integrating 20V Organic CMOS Digital and Analog Circuits with Floating Gate for Process-Variation Compensation and 100V Organic PMOS Rectifier
12.3 - Real-Time Current-Waveform Sensor with Plugless Energy Harvesting from AC Power Lines for Home/Building Energy-Management Systems
12.4 - A 3.9ns 8.9mW 4 4 Silicon Photonic Switch Hybrid Integrated with CMOS Driver
12.5 - A 820GHz SiGe Chipset for Terahertz Active Imaging Applications
12.6 - A 130μA Wake-Up Receiver SoC in 0.13μm CMOS for Reducing Standby Power of An Electric Appliance Controlled by An Infrared Remote Controller
12.7 - Programmable Cell Array Using Rewritable Solid-Electrolyte Switch Integrated in 90nm CMOS
12.8 - 6W/25mm2 Inductive Power Transfer for Non-Contact Wafer-Level Testing
12.9 - GHz-Range Continuous-Time Programmable Digital FIR with Power Dissipation that Automatically Adapts to Signal Activity
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Session 13 - Analog Techniques
13.0 - Session 13 Overview: Analog Technologies
13.1 - A Simple LED Lamp Driver IC with Intelligent Power-Factor Correction
13.2 - A 1.2A Buck-Boost LED Driver with 13% Efficiency Improvement Using Error-Averaged SenseFET-Based Current Sensing
13.3 - Filterless Integrated Class-D Audio Amplifier Achieving 0.0012% THD+N and 96dB PSRR When Supplying 1.2W
13.4 - A 5.9nV/ Hz Chopper Operational Amplifier with 0.78µV Maximum Offset and 28.3nV/°C Offset Drift
13.5 - A Current-Feedback Instrumentation Amplifier with a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error
13.6 - A 6.7nV/ Hz Sub-mHz-1/f-Corner 14b Analog-to-Digital Interface for Rail-to-Rail Precision Voltage Sensing
13.7 - A 36V JFET-Input Bipolar Operational Amplifier with 1µV/°C Maximum Offset Drift and -126dB Total Harmonic Distortion
13.8 - A 3.3V-Supply 120mW Differential ADC Driver Amplifier in 0.18µm SiGe BiCMOS with 108dBc IM3 at 100MHz
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Session 14 - High-Performance Embedded Memory
14.0 - Session 14 Overview: High-Performance Embedded Technology
14.1 - A 64Mb SRAM in 32nm High-k Metal-Gate SOI Technology with 0.7V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
14.2 - A 4R2W Register File for a 2.3GHz Wire-Speed POWERTM Processor with Double-Pumped Write Operation
14.3 - An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
14.4 - A 28nm High-Density 6T SRAM with Optimized Peripheral-Assist Circuits for Operation Down to 0.6V
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Session 15 - High-Performance SoCs & Components
15.0 - Session 15 Overview: High-Performance SoCs & Components
15.1 - A Fully Integrated Multi-CPU, GPU and Memory Controller 32nm Processor
15.2 - An 80Gb/s Dependable Communication SoC with PCI Express I/F and 8 CPUs
15.3 - A Fully-Integrated 3-Level DC/DC Converter for Nanosecond-Scale DVS with Fast Shunt Regulation
15.4 - A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices
15.5 - A Programmable Adaptive Phase-Shifting PLL for Clock Data Compensation Under Resonant Supply Noise
15.6 - A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values
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Session 16 - mm-Wave Design Techniques
16.0 - Session 16 Overview: mm-Wave Design Techniques
16.1 - A 21.7-to-27.8GHz 2.6-Degrees-rms 40mW Frequency Synthesizer in 45nm CMOS for mm-Wave Communication Applications
16.2 - A mm-Wave Quadrature VCO Based on Magnetically Coupled Resonators
16.3 - A 6.5mW Inductorless CMOS Frequency Divider-by-4 Operating up to 70GHz
16.4 - A 60GHz Antenna-Referenced Frequency-Locked Loop in 0.13µm CMOS for Wireless Sensor Networks
16.5 - A 220-to-275GHz Traveling-Wave Frequency Doubler with -6.6dBm Power at 244GHz in 65nm CMOS
16.6 - Distributed Active Radiation for THz Signal Generation
16.7 - A 120GHz 10Gb/s Phase-Modulating Transmitter in 65nm LP CMOS
16.8 - A 1.5GHz-Modulation-Range 10ms-Modulation-Period 180kHzrms-Frequency-Error 26MHz-Reference Mixed-Mode FMCW Synthesizer for mm-Wave Radar Application
16.9 - A Short-Range UWB Impulse-Radio CMOS Sensor for Human Feature Detection
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Session 17 - Biomedical & Displays
17.0 - Session 17 Overview: Biomedical & Displays
17.1 - A 160µW 8-Channel Active Electrode System for EEG Monitoring
17.2 - A 0.013mm2 5µW DC-Coupled Neural Signal Acquisition IC with 0.5V Supply
17.3 - An AC-Powered Optical Receiver Consuming 270μW for Transcutaneous 2Mb/s Data Transfer
17.4 - A Neural Stimulator Front-End with Arbitrary Pulse Shape, HV Compliance and Adaptive Supply Requiring 0.05mm2 in 0.35μm HVCMOS
17.5 - A Low Noise Current Readout Architecture for Fluorescence Detection in Living Subjects
17.6 - A Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor
17.7 - A 160 128 Single-Photon Image Sensor with On-Pixel 55ps 10b Time-to-Digital Converter
17.8 - Bidirectional OLED Microdisplay: Combining Display and Image Sensor Functionality into a Monolithic CMOS Chip
17.9 - A 0.014mm2 9b Switched-Current DAC for AMOLED Mobile Display Drivers
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Session 18 - Organic Innovations
18.0 - Session 18 Overview: Organic Innovations
18.1 - An 8b Organic Microprocessor on Plastic Foil
18.2 - A 3.3V 6b 100kS/s Current-Steering D/A Converter Using Organic Thin-Film Transistors on Glass
18.3 - A 1V Printed Organic DRAM Cell Based on Ion-Gel Gated Transistors with a Sub-10nW-per-Cell Refresh Power
18.4 - Fully Printed Organic CMOS Technology on Plastic Substrates for Digital and Analog Applications
D18_01.pdf
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D18_02.pdf
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D18_03.pdf
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D18_04.pdf
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Session 19 - Low-Power Digital Techniques
19.0 - Session 19 Overview: Low-Power Digital Techniques
19.1 - A Voltage-Scalable Biomedical Signal Processor Running ECG Using 13pJ/cycle at 1MHz and 0.4V
19.2 - An 82µA/MHz Microcontroller with Embedded FeRAM for Energy-Harvesting Applications
19.3 - Comparison of 65nm LP Bulk and LP PD-SOI with Adaptive Power Gate Body Bias for an LDPC Codec
19.4 - A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS
19.5 - A 62mV 0.13µm CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic
19.6 - A 0.27V 30MHz 17.7nJ/transform 1024-pt Complex FFT Core with Super-Pipelining
D19_01.pdf
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D19_02.pdf
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D19_03.pdf
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D19_04.pdf
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D19_05.pdf
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D19_06.pdf
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Session 20 - High-Speed Transceivers & Building Blocks
20.0 - Session 20 Overview: High-Speed Transceivers & Building Blocks
20.1 - A 4-Channel 10.3Gb/s Transceiver with Adaptive Phase Equalizer for 4-to-41dB Loss PCB Channel
20.2 - A 1.0625-to-14.025Gb/s Multimedia Transceiver with Full-rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40nm CMOS
20.3 - Analog-DFE-Based 16Gb/s SerDes in 40nm CMOS That Operates Across 34dB Loss Channels at Nyquist with a Baud Rate CDR and 1.2Vpp Voltage-Mode Driver
20.4 - An 8.4mW/Gb/s 4-Lane 48Gb/s Multi-Standard-Compliant Transceiver in 40nm Digital CMOS Technology
20.5 - A Pattern-Guided Adaptive Equalizer in 65nm CMOS
20.6 - A 6Gb/s Receiver with 32.7dB Adaptive DFE-IIR Equalization
20.7 - A 5.4Gb/s Adaptive Equalizer Using Asynchronous-Sampling Histograms
20.8 - A 0.076mm2 3.5GHz Spread-Spectrum Clock Generator with Memoryless Newton-Raphson Modulation Profile in 0.13µm CMOS
D20_01.pdf
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D20_02.pdf
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D20_03.pdf
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D20_04.pdf
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D20_05.pdf
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D20_06.pdf
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D20_07.pdf
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D20_08.pdf
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Session 21 - Cellular
21.0 - Session 21 Overview: Cellular
21.1 - A SAW-less GSM/GPRS/EDGE Receiver Embedded in a 65nm CMOS SoC
21.2 - A 9-Band WCDMA/EDGE Transceiver Supporting HSPA Evolution
21.3 - A 65nm CMOS SoC with Embedded HSDPA/EDGE Transceiver, Digital Baseband and Multimedia Processor
21.4 - A Receiver for WCDMA/EDGE Mobile Phones with Inductorless Front-End in 65nm CMOS
21.5 - A Compact SAW-less Multiband WCDMA/GPS Receiver Front-End with Translational Loop for Input Matching
21.6 - A Multiband LTE SAW-less Modulator with -160dBc/Hz RX-Band Noise in 40nm LP CMOS
21.7 - A Fully Digital Multimode Polar Transmitter Employing 17b RF DAC in 3G Mode
21.8 - A Low-Power Wideband Polar Transmitter for 3G Applications
D21_01.pdf
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D21_02.pdf
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D21_03.pdf
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D21_04.pdf
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D21_05.pdf
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D21_06.pdf
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D21_07.pdf
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D21_08.pdf
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Session 22 - DC/DC Converters
22.0 - Session 22 Overview: DC/DC Converters
22.1 - A Fully Integrated Power-Management Solution for a 65nm CMOS Cellular Handset Chip
22.2 - A Digitally Controlled DC-DC Converter for SoC in 28nm CMOS
22.3 - 20µA to 100mA DC-DC Converter with 2.8 to 4.2V Battery Supply for Portable Applications in 45nm CMOS
22.4 - A Digitally Controlled DC-DC Buck Converter with Lossless Load-Current Sensing and BIST Functionality
22.5 - Zero-Order Control of Boost DC-DC Converter with Transient Enhancement Using Residual Current
22.6 - Robust and Efficient Synchronous Buck Converter with Near-Optimal Dead-Time Control
22.7 - A 90% Peak Efficiency Single-Inductor Dual-Output Buck-Boost Converter with Extended-PWM Control
22.8 - Spurious-Noise-Free Buck Regulator for Direct Powering of Analog/RF Loads Using PWM Control with Random Frequency Hopping and Random Phase Chopping
D22_01.pdf
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D22_02.pdf
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D22_03.pdf
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D22_04.pdf
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D22_05.pdf
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D22_06.pdf
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D22_07.pdf
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D22_08.pdf
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Session 23 - Image Sensors
23.0 - Session 23 Overview: Image Sensors
23.1 - An 80μVrms-Temporal-Noise 82dB-Dynamic-Range CMOS Image Sensor with a 13-to-19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC
23.2 - A Sub-Electron Readout Noise CMOS Image Sensor with Pixel-Level Open-Loop Voltage Amplification
23.3 - A 320 256 90dB SNR and 25µm-Pixel-Pitch Infrared Image Sensor
23.4 - A 16 Mfps 165kpixel Backside-Illuminated CCD
23.5 - A 300mm Wafer-Size CMOS Image Sensor with In-Pixel Voltage-Gain Amplifier and Column-Level Differential Readout Circuitry
23.6 - A 128 96 Pixel Event-Driven Phase-Domain ΔΣ-Based Fully Digital 3D Camera in 0.13μm CMOS Imaging Technology
23.7 - An Angle-Sensitive CMOS Imager for Single-Sensor 3D Photography
23.8 - A 1/13-inch 30fps VGA SoC CMOS Image Sensor with Shared Reset and Transfer-Gate Pixel Control
23.9 - A 1/2.33-inch 14.6M 1.4µm-Pixel Backside-Illuminated CMOS Image Sensor with Floating Diffusion Boosting
D23_01.pdf
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D23_02.pdf
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D23_03.pdf
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D23_04.pdf
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D23_05.pdf
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D23_06.pdf
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D23_07.pdf
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D23_08.pdf
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D23_10.pdf
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D23_11.pdf
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Session 24 - Transmitter Blocks
24.0 - Session 24 Overview: Transmitter Blocks
24.1 - A 40nm Wideband Direct-Conversion Transmitter with Sub-Sampling-Based Output Power, LO Feedthrough and I/Q Imbalance Calibration
24.2 - A Flip-Chip-Packaged 1.8V 28dBm Class-AB Power Amplifier with Shielded Concentric Transformers in 32nm SoC CMOS
24.3 - A Switched-Capacitor Power Amplifier for EER/Polar Transmitters
24.4 - An EDGE/GSM Quad-Band CMOS Power Amplifier
24.5 - A Compact 1V 18.6dBm 60GHz Power Amplifier in 65nm CMOS
D24_01.pdf
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D24_02.pdf
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D24_03.pdf
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D24_04.pdf
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D24_05.pdf
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Session 25 - CDRs & Equalization Techniques
25.0 - Session 25 Overview: CDRs & Equalization Techniques
25.1 - A 5Gb/s Adaptive DFE for 2 Blind ADC-Based CDR in 65nm CMOS
25.2 - A 0.5-to-2.5Gb/s Reference-less Half-Rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
25.3 - A TDC-less 7mW 2.5Gb/s Digital CDR with Linear Loop Dynamics and Offset-Free Data Recovery
25.4 - A Digital Wideband CDR with ±15.6kppm Frequency Tracking at 8Gb/s in 40nm CMOS
25.5 - A 20Gb/s Digitally Adaptive Equalizer/DFE with Blind Sampling
25.6 - A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation
25.7 - A 10Gb/s Half-UI IIR-Tap Transmitter in 40nm CMOS
25.8 - A 13.8mW 3.0Gb/s Clock-Embedded Video Interface with DLL-Based Data-Recovery Circuit
D25_01.pdf
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D25_02.pdf
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D25_03.pdf
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D25_04.pdf
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D25_05.pdf
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D25_06.pdf
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D25_07.pdf
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D25_08.pdf
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Session 26 - Low-Power Wireless
26.0 - Session 26 Overview: Low-Power Wireless
26.1 - A 7.9µW Remotely Powered Addressed Sensor Node Using EPC HF and UHF RFID Technology with -10.3dBm Sensitivity
26.2 - An Isolator-less CMOS RF Front-End for UHF Mobile RFID Reader
26.3 - A 2.4GHz ULP OOK Single-Chip Transceiver for Healthcare Applications
26.4 - A 120µW MICS/ISM-Band FSK Receiver with a 44µW Low-Power Mode Based on Injection-Locking and 9x Frequency Multiplication
26.5 - A GPS/Galileo SoC with Adaptive In-Band Blocker Cancellation in 65nm CMOS
26.6 - A 0.05-to-10GHz 19-to-22GHz and 38-to-44GHz SDR Frequency Synthesizer in 0.13µm CMOS
26.7 - A 4.6GHz MDLL with -46dBc Reference Spur and Aperture Position Tuning
D26_01.pdf
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D26_02.pdf
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D26_03.pdf
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D26_04.pdf
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D26_05.pdf
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D26_06.pdf
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D26_07.pdf
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Session 27 - Oversampling Converters
27.0 - Session 27 Overview: Oversampling Converters
27.1 - A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW
27.2 - An 8mW 50MS/s CT ΔΣ Modulator with 81dB SFDR and Digital Background DAC Linearization
27.3 - A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bidirectional Single-Slope Quantizer
27.4 - A 250mV 7.5µW 61dB SNDR CMOS SC ΔΣ Modulator Using a Near-Threshold-Voltage-Biased CMOS Inverter Technique
27.5 - A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140µW
27.6 - A 1.7mW 11b 1-1-1 MASH ΔΣ Time-to-Digital Converter
27.7 - A 120dB-SNR 100dB-THD+N 21.5mW/Channel Multibit CT ΔΣ DAC
27.8 - A 108dB-DR 120dB-THD and 0.5Vrms Output Audio DAC with Inter-Symbol-Interference-Shaping Algorithm in 45nm CMOS
D27_01.pdf
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D27_02.pdf
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D27_03.pdf
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D27_04.pdf
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D27_05.pdf
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D27_06.pdf
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D27_07.pdf
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D27_08.pdf
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Session 28 - DRAM & High-Speed I/O
28.0 - Session 28 Overview: DRAM & High-Speed I/O
28.1 - An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Simultaneous Bidirectional Dual (Base+RF)-Band Signaling
28.2 - A 2.7Gb/s/mm2 0.9pJ/b/Chip 1Coil/Channel ThruChip Interface with Coupled-Resonator-Based CDR for NAND Flash Memory Stacking
28.3 - A 12Gb/s Non-Contact Interface with Coupled Transmission Lines
28.4 - A 4.8Gb/s Impedance-Matched Bidirectional Multi-Drop Transceiver for High-Capacity Memory Interface
28.5 - A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4 128 I/Os Using TSV-Based Stacking
28.6 - A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a Programmable DQ Ordering Crosstalk Equalizer and Adjustable Clock-Tracking BW
28.7 - A 58nm 1.8V 1Gb PRAM with 6.4MB/s Program BW
28.8 - A 1.6V 1.4Gb/s/pin Consumer DRAM with Self-Dynamic Voltage-Scaling Technique in 44nm CMOS Technology
28.9 - An Embedded DRAM Technology for High-Performance NAND Flash Memories
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D28_02.pdf
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D28_03.pdf
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D28_04.pdf
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D28_07.pdf
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D28_08.pdf
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D28_09.pdf
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D28_10.pdf
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Forums
F1: Advanced Transmitters for Wireless Infrastructure
F2: Ultra-Low Voltage VLSIs for Energy Efficient Systems
F3: Towards Personalized Medicine and Monitoring for Healthy Living
F4: Design of "Green" High-Performance Processor Circuits
F5: Image Sensors for 3D Capture
F6: High-Speed Transceivers: Standards, Challenges, and Future
F_01.pdf
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F_02.pdf
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F_03.pdf
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F_04.pdf
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F_05.pdf
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F_06.pdf
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Evening Panels
EP1: Good, Bad, Ugly - 20 Years of Broadband Evolution: What's Next?
EP2: 20-22nm Technology Options and Design Implications
EP_01.pdf
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EP_02.pdf
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Special Evening Topics
ES0: Student Research Preview
ES1: Data Converter Breakthroughs in Retrospect
ES2: Wireless Sensor Systems: Solution & Technology
ES3: Future System and Memory Architectures: Transformations by Technology and Applications
ES4: Body Area Network: Technology, Solutions, and Standardization
ES5: Gb/s+ Portable Wireless Communications
ES6: Technologies for Smart Grid and Smart Meter
ES_00.pdf
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ES_01.pdf
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ES_02.pdf
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ES_03.pdf
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ES_05.pdf
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ES_06.pdf
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所有Session 的Overview：
Session_01ov.pdf
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Session_02ov.pdf
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Session_03ov.pdf
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Session_05ov.pdf
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Session_06ov.pdf
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Session_07ov.pdf
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Session_08ov.pdf
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Session_09ov.pdf
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Session_10ov.pdf
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Session_11ov.pdf
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Session_12ov.pdf
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Session_13ov.pdf
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Session_14ov.pdf
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Session_15ov.pdf
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Session_16ov.pdf
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Session_17ov.pdf
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Session_18ov.pdf
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Session_19ov.pdf
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Session_20ov.pdf
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Session_21ov.pdf
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Session_22ov.pdf
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Session_23ov.pdf
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Session_24ov.pdf
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Session_25ov.pdf
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Session_26ov.pdf
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Session_27ov.pdf
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Session_28ov.pdf
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