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发表于 2010-8-11 09:15:41
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我有两个问题向老扁兄请教(中文版没有保存,只好英文版):
1.AMBA 2.0 spec, figure3-17 Data bus ownership.(本帖36楼)
the T7 clock edge, is the last data phase for Master1(M1) and the first address phase for Master2(M2). I have dount about the HREADY signal.
1.1 if M1 and M2 access the same slave(S1), The HREADY is drive by the S1, the handover is ok.
1.2 if M1 access Slave1(S1) and M2 access Slave2(S2), then the HREADY in T7 should drived by S1, and T7 is the last data phase of M1-S1. The first address phase of M2-S2 should after T7. The figure 3-17 is wrong in this case.
so I guess the HREADY to each Master is independent. not like the HRDATA which is a common bus signal for each master. Am I right?
2. in AMBA 2.0, APB slave has no response signals, if slave can't finish the R/W request from APB Master, then what? How to guratee the slave can accept every request from Master?
(http://bbs.eetop.cn/thread-263470-1-1.html)
老扁兄给出的回答:
Hready只针对data phase,所以你的第一个理解有误。第二个问题,hready就是很好的握手信号。当然amba应用时最好不要只靠hready,应该先通过系统级中断来启动总线传输,这样效率最好。另外,有问题最好在帖子上,这样我们的讨论就可以被所有人看到,谢谢!
我的继续追问:
1. 既然HREADY 只针对data phase, 为什么T7之后,M2驱动的HADDR变成了B+4,我的理解是,M2在T7看到了HREADY=1,所以M2把地址往前+4。所以:T7时的HREADY=1,既是M1 的最后一个data phase 的enable 信号,又是M2的第一个address phase 的enable 信号。我的疑问就是,如果M1访问S1,M2访问S2,那怎么T7时的HREADY由哪个slave来驱动。
2. AMBA2.0 的APB中,slave没有response信号,那如果slave不能响应APB Bridge发来的R/W请求,那么write data 写不进去,read data 也没有啊。这种情况该怎么办呢?有什么报错机制? |
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