射频电路和射频集成电路设计中的关键课题

contral

出版社: 高等教育出版社; 第1版 (2005年2月1日)
外文书名: Key Issues in RF/RFIC Circuit Design
平装: 395页
正文语种: 英语
开本: 16

内容简介回到顶部↑本书着重论述和强调在射频电路和射频集成电路设计中的共同的关键性课题。内容包括：射频和射频集成电路设计的核心部份:阻抗匹配；基本射频参数和方程式；射频接地；从单端线路到差分线路；容许误差分析；射频集成电路设计中的难题；低噪声放大器设计的讨论。本书的读者对象是大学的高年级学生、研究生和工程技术人员。
目录回到顶部↑
Chapter 1 Importance of Impedance Matching .
1.1 Difference between RF and Digital Circuit Design
1.1.1 Case h Digital Circuits at Low Data Rate
1.1.2 Case 2: Digital Circuits at High Data Rate
1.2 Significance of Impedance Matching
1.2.1 Power Transportation from a Source to a Load
1.2.2 Maximizing of Power Transportation without Phase Shift
1.2.3 Conjugate Impedance Matching and Voltage Reflection Coefficient
1.2.4 Impedance Matching Network
1.3 Problems due to Unmatched Status of Impedance
1.3.1 General Expression of Power Transportation
1.3.2 Power Instability and Additional Power Loss
1.3.3 Additional Distortion and Quasi-Noise
1.3.4 Power Measurement
1.3.5 Power Transportation and Voltage Transportation
1.3.6 Burning of a Transistor
References
Chapter 2 Impedance Matching
2.1 Impedance Measured by Small Signal
2.1.1 Impedance Measured by S Parameter Measurement
.2.1.2 Smith Chart: Impedance and Admittance Coordination
2.1.3 Accuracy of Smith Chart
2.1.4 Relationship between the Impedance in Series and in Parallel
2.2 Impedance Measured by Large Signal
2.3 Impedance Matching
2.3.1 One Part Matching Network
2.3.2 Recognition of Regions in a Smith Chart
2.3.3 Two Parts Matching Network
2.3.4 Two Parts Upward and Downward Impedance Transformer
2.3.5 Three Parts Matching Network and Impedance Transformer
2.3.5.1 Topology Limitation of Two Parts Matching Network
2.3.5.2 FI Type Matching Network
2.3.5.3 TType Matching Network
2.4 Some Useful Schemes for Impedance Matching
2.4.1 Designs and Tests when ZL is not 50Ω
2.4.2 Conversion between T and Fl Type Matching Network
2.4.3 Parts in a Matching Network
2.4.4 Impedance Matching between Power Transportation Units
2.4.5 Impedance Matching for a Mixer
References
Chapter 3 RF Grounding
3.1 A True Story.
3.2 Three Components for RF Grounding
3.2.1 "Zero" Capacitors
3.2.2 Micro Strip Line
3.2.3 RF Cables
3.3 Examples of RF Grounding
3.3.1 TestPCB
3.3.1.1 Small Test PCB
3.3.1.1.1 Basic Types of Test PCB.
3.3.1.1.2 RF Grounding with a Rectangular Metallic Frame
3.3.1.1.3 An Example
3.3.1.2 Large Test PCB
3.3.1.2.1 RF Grounding by "Zero" Chip Capacitors
3.3.1.2.2 RF Grounding by Runners with Half or Quarter Wavelength
3.3.2 Isolation between Input and Output in a Mixer or an Up-converter
3.3.3 Calibration for Network Analyzer
3.4 RF Grounding for Reduction of Return Current Coupling
3.4.1 A Circuit Built by Discrete Parts on a PCB
3.4.2 RFICs
References
Chapter 4 Equivalent Circuits of Passive Chip Parts
4.1 Modeling of Passive Chip Parts
4.2 Characterization of a Chip Part by Network Analyzer
4.3 Extraction from the Measurement by Network Analyzer
4.3.1 Extraction for Chip Capacitors
4.3.2 Extraction for Chip Inductors
4.3.3 Extraction for Chip Resistors
4.4 Summary
References
Chapter 5 Single-ended Stage and Differential Pair
5.1 Basic Single-ended Stage
5.1.1 General Description
5.1.2 Small Signal Model of a Bipolar Transistor
5.1.2.1 Impedance of a CE (Common Emitter) Device
5.1.2.2 Impedance of a CB (Common Base) Device
5.1.2.3 Impedance of a CC (Common Collector) Device
5.1.2.4 Comparison between CE, CB, and CC Device
5.1.3 Small-signal Model of a MOSFET
5.1.3.1 Impedance of a CS (Common Source) Device
5.1.3.2 Impedance of a CG (Common Gate) Device
5.1.3.3 Impedance of a CD (Common Drain) Device
5.1.3.4 Comparison between CS, CG, and CD Device
5.2 Differential Pair
5.2.1 DC Transfer Characteristic
5.2.1.1 DC Transfer Characteristic of a Bipolar Differential Pair
5.2.1.2 DC Transfer Characteristic of a CMOS Differential Pair
5.2.2 Small Signal Characteristic
5.2.3 Improvement of CMRR
5.2.4 Increase of Voltage Swing
5.2.5 Cancellation of Interference
5.2.6 Noise in a Differential Pair
5.3 Apparent Difference between Single-ended Stage and Differential Pair
5.4 DC Offset
5.4.1 DC Offset in a Single-ended Device
5.4.2 Zero DC Offset in a Pseudo-Differential Pair
5.4.3 Why "Zero" IF or Direct Conversion
5.4.4 DC Offset Cancellation
5.4.4.1 "Chopping" Mixer
5.4.4.2 DC Offset Calibration
5.4.4.3 Hardware Schemes
References ..
Chapter 6 Balun
6.1 Coaxial Cable Balnn
6.2 Ring Micro Strip Line Balun
6.3 Transformer Balun
6.4 Transformer Balun Composed by Two
Stacked 2x2 Transformers
6.5 LC Balun
References
Chapter 7 Tolerance Analysis
7.1 Importance of Tolerance Analysis
7.2 Fundamentals of Tolerance Analysis
7.2.1 Tolerance and Normal Distribution
7.2.2 6a, Cp, and Cpk
7.2.3 Yield Rate and DPU
7.2.4 Poisson Distribution
7.3 An Approach to 6a Design and Production
7.4 An Example: A Tunable Filter Design
7.4.1 Description of the Tunable Filter Design
7.4.2 Monte-Carlo Analysis
7.5 Appendix: Table of the Normal Distribution
References
Chapter 8 Prospect of RFIC Design
8.1 History of RFIC Development
8.2 Isolation between Blocks in an RFIC
8.2.1 Definition and Measurement of Isolation
8.2.2 Isolation Technology
8.3 Low Q Value of Spiral Inductor
8.3.1 Skin Effect
8.3.2 Attenuation due to Substrate
8.3.3 Flux Leakage
8.3.4 Flux Cancellation
8.3.5 A Possible Solution--Negative Resistance Compensation
8.3.5.1 Negative Resistance Generator with a FET
8.3.5.2 Negative Resistance Generator with Transformer
8.4 Layout
8.4.1 Runners
8.4.2 Parts
8.4.3 Variable Parts in RFIC
8.4.4 Symmetry
8.4.5 Via
8.4.6 Free Space on the Die
8.5 Two Challenges in an RFIC or SOC Design
8.5.1 Isolation
8.5.2 High Q Inductor for IC
References
Chapter 9 Noise, Gain, and Sensitivity of a Receiver
9.1 Noise in a Circuit Block or a System
9.1.1 Noise Sources
9.1.1.1 Shot Noise
9.1.1.2 Thermal Noise
9.1.1.3 Flicker Noise (I/f Noise)
9.1.2 Definition of Noise Figure
9.1.3 Noise Figure in a Noisy Two-Port Block
9.1.4 Minimum Noise Figure and Equivalent Noise Resistor
9.1.4.1 Noise in a MOSFET
9.1.4.2 Noise in a Bipolar Device
9.2 Gain
9.2.1 Definition of Power Gains
9.2.2 Power Gain and Voltage Gain
9.3 Sensitivity
9.3.1 Standard Noise Source
9.3.2 Equivalent Input Noise
9.3.3 Sensitivity of a Receiver
References
Chapter 10 Non-linearity and Spurious Products
10.1 Spurious Products
10.1.1 Harmonics
10.1.2 Complicated Spurious Products
10.2 IP (Intercept Point) and IMR (Inter-Modulation Rejection)
10.3 3rd Order Intercept Point and Spurious Product
10.4 1 dB Compression Point and IP3
10.5 2na Order Intercept Point and Spurious Product
10.6 Distortion
References
Chapter 11 Cascaded Equations and System Analysis
11.1 Cascaded Equation for Power Gain
11.2 Cascaded Equation for Noise Figure
11.3 Cascaded Equation for Intercept Point
11.4 Application of Cascaded Equations in the System Analysis
References
Chapter 12 From Analog to Digital Communication System
12.1 Modulation in an Analog Communication System
12.2 Encoding in a Digital Communication System
12.2.1 NRZ and Manchester Format
12.2.2 BPSK
12.2.3 QPSK, OQPSK, MSK
12.2.4 FSK, CPFSK
12.3 Decoding and Bit-Error Probability
12.4 Error Correction Schemes
References ...

chujn

下来看看，谢谢。

jianhua123

谢谢分享

tiger2031573

xiexie

cp1927

thank a lot

dclustc

谢谢，thanks

lihongpengtd

哎，已经买了~~

xfchen

THANKS FOR SHARE

planitia

Thanks!

contral

好书不能沉了