A Very Low Power SAR Analog to Digital Converter

angelweishan

A Very Low Power SAR Analog to Digital Converter
Includes two Matlab codes to calculate INL, DNL and SNR

Contents
Abstract.............................................III
Contents.............................................IV
List of Figures........................................V
List of Tables...................................................VI

1 Introduction.........................................- 1 -
1.1 Thesis Organization.........................................- 1 -

2 ADC Architectures..................................- 2 -
2.1 Topologies Comparison...........................................- 3 -
2.2 Successive Approximation Register ADC......................- 6 -

3 Behavioural Model..............................................................- 8 -
3.1 ADC Parameters................................................- 8 -
3.2 Simulink Model.....................................................- 9 -
3.3 Simulations Results...................................................- 12 -

4 SAR ADC Building Blocks.................................................- 13 -
4.1 90nm CMOS Technology....................................- 13 -
4.2 Fully Differential vs. Single Ended................................- 14 -
4.3 Digital to Analog Converter DAC Topologies................- 15 -
4.3.1 Binary Weighted Switched Capacitor Array DAC.................- 15 -
4.3.2 Junction-Splitting Capacitor Array...............................- 17 -
4.3.3 Energy Efficient Charge-Redistribution DAC.............- 19 -
4.3.4 Serial Charge Redistribution D/A Converter............- 20 -
4.3.5 Circuit Choice and Design..............................- 21 -
4.4 Comparator..............................................- 24 -
4.4.1 Subthreshold Source-Coupled Logic........................- 25 -
4.4.2 Design Approach..............................................- 26 -
4.4.3 Matching Considerations....................................- 28 -
4.4.4 Circuit implementation.....................................- 30 -
4.5 Level shifter........................................................- 33 -
4.6 Track and Hold..............................................- 33 -
4.7 Delay Cell.........................................................- 35 -
4.8 SAR Logic.........................................- 36 -
4.8.1 VHDL Code....................................................- 36 -
4.8.2 Synthesis....................................................- 41 -
4.8.3 Place & Route...........................................- 44 -

5 Experimental Results............................................- 45 -
5.1 Comparator........................................................- 45 -
5.2 Mismatch effects on ADC parameters...................- 47 -
5.3 Signal to Noise Ratio.............................................- 48 -
5.4 DAC...................................................- 49 -
5.5 Input/Output Characteristic........................................- 50 -
5.6 Current and power considerations........................- 52 -

6 Conclusions.......................................................- 55 -
6.1 Future work.....................................................- 56 -
References.........................................................- 57 -

Design of a Very Low Power SAR ADC
Appendix I…………………………………………………………………………-60-
Appendix II……………………………………………………………………..-63-
Appendix III…………………………………………………………………….-67-
Appendix IV……………………………………………………………………….-70-
Appendix V……………………………………………………………………….-71-
Appendix VI……………………………………………………………………….-75-

Matlab code for INL and DNL calculation:
clc
clear all
% Basic
Ut = 0.026;
Vsw = 10*Ut;
nn = 1.3;
ISS = 1e-9; % tail bias
% ADC
NF = 8; % num. bit
N = 2^NF; % fft points
FS = 1; % full scale
dV = FS/2^NF;
LSB = FS/N;
Vr = 1;
fs = 2^13; % sampling freq.
tck = 1/fs; % sampling period
fsh = fs/9; % sampling freq.
tsh = 1/fsh; % sampling period
% Input signal
Vin = 0.7;
Vref = FS;
Vss = 0;
Ain = 0.5; % sin wave amplitude
fin = fs/2^12; % sin wave freq
start_ramp=0;
offset_sin=0.5;
Vcin1 = 1; % =1->ramp ; =0->sin (if Vcin2=0)
Vcsah = 0; % Vcsah = 0 : SAH is employed
g_comp = 10000; % gain of comparator preamplifier
noise = 0; % white noise at comparator input
off_comp = 0; % offset of comparator
comp_val = 0.5; % limit of comparison
% Simulation
M = 2^12; % sample points
ts = 0.001*tck; % sim. time for unit delay
%tf = (6 + M)/(fs*2); % sim. final time
slope=(1/N)/(4*LSB);
stop_sim=1;

% DAC capacitances and voltages--mismatched
index=1;
tr=100;
var_cap=0;
vfin=0.01;
step=vfin/5;

while var_cap<=vfin
for turns=1:tr
Cdac = 0;
c0 = 24e-15;
for i=1:8

cap_id(i) = c0 * 2^(i-1);

cap(i) = c0*2^(i-1) + var_cap*cap_id(i)*randn(1);
end
Cdac = sum(cap)+c0;
Cdac_id= sum(cap_id)+c0;
for j=1:8

Vdac(j)=cap(j)/Cdac;

Vdac_id(j)=cap_id(j)/Cdac_id;
end

% run simulation

tout = sim('SAR_ADC_inldnl');
load('o_adc_di.mat');
out_adc_a=o_adc(2,';
x_adc=o_adc(1,';
load('o_sah_di.mat');
out_sah=o_sah(2,';
load('in_sh_di.mat');
in_shape=in_sh(2,:)';
load('o_adc_dig.mat');
y_adc_d=o_adc_dig';

fin=max(size(y_adc_d));
out_adc=zeros(fin,1);

for ii=1:fin

for jj=1:8

out_adc(ii) = out_adc(ii)+y_adc_d(ii,jj+1)*Vdac_id(jj);

end
end

i=1;
while x_adc(i)<(tsh)

i=i+1;
end
l=max(size(out_adc));
out_adc=out_adc(i:l);
l1=l-i+1;
x_adc=x_adc(1:l1);
out_sah=out_sah(1:l1);
in_shape=in_shape(1:l1);
y=out_adc;
x=in_shape;
out_ch=[x y];

% dnl and inl ADC output
% input y contains the ADC output vs time
min_v=min(y);
max_v=max(y);
x1=min_vSB:max_v;
l=numel(x1);

% histogram
h = hist(y,x1);

n_elem =histc(y,x1);

% cumulative histogram
ch = cumsum(h);

dnl=0;
v_real=zeros(l-1,1);
n=0;
n_old=0;
x1=x1(1:l-1);
for i=1:l-1

if i==1

n=ch(i);

n_old=1;

v_real(i)=out_ch(n,1);

else

n_old=n;

n=ch(i);

v_real(i)=out_ch(n,1)-out_ch(n_old,1);

end



dnl(i) = (v_real(i)-LSB)/LSB;
end

misscodes = length(find(dnl<-0.9));
%
% calculate inl
inl=zeros(size(dnl));
for j=1:size(inl')

inl(j)=sum(dnl(1:j));
%INL,j=DNL,0+DNL,1+...+DNL,j

% INL=inl(j);
end
inl_turn(turns)=max(abs(inl));
dnl_turn(turns)=max(abs(dnl));
end

INL(index)=mean(inl_turn);
DNL(index)=mean(dnl_turn);
xax(index)=var_cap;
index=index+1;
var_cap = var_cap + step;

end

figure(1)
clf
subplot(211)
plot([1:2^NF],DNL,'--rs','MarkerEdgeColor','k','MarkerFaceColor','g','MarkerSize',10);
grid on;
title('MAX DIFFERENTIAL NONLINEARITY vs. VARIANCE_ERROR_CAP');
xlabel('VARIANCE_ERROR_CAP');
ylabel('DNL (LSB)');
hold on
subplot(212)
plot([1:2^NF],INL);
grid on;
title('MAX INTEGRAL NONLINEARITY vs. VARIANCE_ERROR_CAP');
xlabel('VARIANCE_ERROR_CAP');
ylabel('INL(LSB)');
hold on
-

nymph777

thanks

lyly

看看是谁的论文

myota

看看！！

liuzhieetop

下来学习一下，谢了

gemini06061978

thanks for sharing

angelweishan

thanks for sharing

casper_xu

需要学习啊 谢谢

s8553warrior

下来学习一下，谢了

robicyang

ding ding ding