|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
本帖最后由 robin_li 于 2010-3-31 11:03 编辑
Title: Senior Design Verification Engineer
Location: Shanghai
Preferred Experience:
-Major in CS or EE and have Master degree or higher
-3 years beyond working experience on ASIC design verification
-Must have strong background on video encoding/decoding algorithms
-Must be proficient in C++ programming and debugging in Linux and Windows platforms. Know well about SW engineering.
-Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools.
-Must be skillful in shell/perl/tcl/Makefile programming in linux OS.
-Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools
-Good English hearing, speaking, reading and writing capabilities.
-Will be a big plus if having tape‐out experience
JOB TITLE: Senior Design Engineer
Location: Shanghai
Preferred Experience:
-Major in EE and have Master degree or higher
-3 years beyond working experience on ASIC design
-Must have strong background on video encoding/decoding algorithms
-Must be proficient in Verilog coding, debugging and modeling
-Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
-Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
-Must be familiar with verification methodologies for from block level to SoC level.
-Should be familiar with shell/perl/tcl programming in linux OS.
-Should be familiar with P&R and Manufacture tech.
-Good English hearing, speaking, reading and writing capabilities.
-Will be a big plus if having tape‐out experience.
-Will be a plus if having C/C++, matlab experience
Title: Sr. DFT Engineer
Location: Shanghai
PREFERRED EXPERIENCE:
-Master of EE or above. New graduate considered.
-Knowledge of Digital design, IC design methodology and Concepts of design for test.
-Be familiar with verilog language
-Be familiar with Unix and TCL, cshell , Perl scripts.
-Strong debug abilities.
-Good Englisth communication skills
-Self-motivated and good team player.
Title: Sr. Physical Design Engineer
Location: Shanghai
PREFERRED EXPERIENCE：
-PhD with 1+ years of industrial experience or MSEE with 3+ years of industrial experience in ASIC design
-Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure.
-Successfully gone through complete product development cycle. Good analytical and debugging skills
-Good listening, writing and speaking English.
-Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
-Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
-Familiar with Front-End EDA tools or circuit design is a plus
-Familiar with Unix/Linux environment and good at scripts
大家感兴趣可以跟我联系，了解详细职位信息
E-mail & MSN : milujite@msn.com
|
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-3-9 14:48:45
楼主
