440页 Cadence 培训教程 Analog Design Environment Lab Manual

hi_china59 · 发表于 2009-9-4 22:08:45

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440页 Cadence 培训教程 Analog Design Environment Lab Manual
This is "Cadence Analog Design Environment Lab Manual" instead of "User Guide"
440 pages
3 rar files

339页 Cadence 培训教程 Analog Design Environment  Lecture Manual
Please visit the following website
http://www.eetop.cn/bbs/thread-194517-1-1.html

Cadence Analog Design Environment Lab Manual

Table of Contents

Module 1: Introduction
      Lab 1-1 Getting Started
      Lab 1-2 Top-Down System Modeling

Module 2: Schematic Capture
      Lab 2-1 Schematic Entry
      Lab 2-2 Symbol Creation
      Lab 2-3 Building the Supply Circuit
      Lab 2-4 Building the ampTest Design

Module 3: Analog Simulation with Spectre Direct
      Lab 3-1 Running Simulation
      Lab 3-2 Using the Stimulus Template
      Lab 3-3 Transient Operating Point Analysis, "infotimes"
      Lab 3-4 Captab

Module 4: Displaying Simulation Results
      Lab 4-1 Displaying Results with the Waveform Window
      Lab 4-2 Saving the Simulation Session
      Lab 4-3 Displaying Interpreted Labels Near Schematic Components
      Lab 4-4 Annotating Simulation Results to the Schematic Window

Module 5: Analyzing Simulation Results
      Lab 5-1 The Waveform Calculator
      Lab 5-2 Managing Simulation Results
      Lab 5-3 Managing Simulation Data with the Results Browser
      Lab 5-4 Viewing Circuit Conditions
      Lab 5-5 Using the Spectre Sweep Feature
      Lab 5-6 Stability Analysis

Module 6: Using OCEAN and SKILL
      Lab 6-1 Using an OCEAN Script to Run a Simple Simulation
      Lab 6-2 Measuring PSRR and CMRR wit OCEAN
      Lab 6-3 Introduction to SKILL
      Lab 6-4 SKILL Development Tools

Module 7: Parametric Analysis Tool
      Lab 7-1: Running Parametric Analysis

Module 8: Corners Analysis Tool
      Lab 8-1: Using the Corner Analysis Tool

Module 9: Monte Carlo Analysis
      Lab 9-1 Monte Carlo Analysis

Module 10: Circuit Optimization Tool
      Lab 10-1 Running Optimization Analysis

Module 11: Exploring CDF
      Lab 11-1: The CDF User Interface
      Lab 11-2: CDF Effects in Simulation

Module 12: Inline Subcircuits
      Lab 12-1: Creating a Parasitic Transistor Model
      Lab 12-2: Using Subcircuit Cells
      Lab 12-3: Adding a Subcircuit Representation

Module 13: Inherited Connections
      Lab 13-1: Inherited Connections
      Lab 13-2: Using Inherited Connections with the ampTest Design

Module 14: Hierarchy Editor
      Lab 14-1: Creating a Configuration File with the Hierarchy Editor
      Lab 14-2: Running a Simulation with Subcircuits
      Lab 14-3: Rerunning Simulation with the Schematic View

Module 15: Parasitic Simulation Setup
      Lab 15-1 Simulating a Schematic Without Parasitic

Module 16: Parasitic Simulation Setup and Analysis
      Lab 16-1: Parasitic Simulation Flow

Appendix A: Diva Parasitic Extraction and Simulation
      Lab A-1: Simulation a Schematic with Parasitics Using the Diva Layout Flow

Appendix B: Using the WaveScan Tool
      Lab B-1: Using the WaveScan Tool

Appendix C: Spectre MDL
      Lab C-1: Using Spectre MDL

Appendix D: Using "dcmatch" Analysis
      Lab D-1: dcmatch

Appendix E: Advanced Topics
      Lab E-1: Verilog-A Overview

[ 本帖最后由 hi_china59 于 2009-9-12 09:06 编辑 ]