Verilog-A language reference manual (june 2009)

xiwang

这是目前最新版的参考手册。

hahalucky

挺好的东西，咋没有人顶呢？

cad14

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iamlvhang

很需要，谢谢

cherryknight

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xshx111

Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.
Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL(an IEEE standard), which was absorbing analog capability from otherlanguages (e.g. MAST). Open Verilog International (OVI, the body thatoriginally standardized Verilog) agreed to support the standardization,provided that it was part of a plan to create Verilog-AMS — a singlelanguage covering both analog and digital design. Verilog-A was anall-analog subset of Verilog-AMS that was the first phase of the project.
Unfortunately, there was considerable delay between the first Verilog-A LRM and the full Verilog-AMS,and in that time Verilog moved to the IEEE, leaving Verilog-AMS behindat Accellera. Hence, the original goal of a single language standard isstill to be achieved.

vency2008

新版下载学习，希望有用

ccp106

谢谢LZ分享啊

helloczt

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jackal0716

thanks a lot~~