|
|
楼主 |
发表于 2006-11-27 08:37:45
|
显示全部楼层
PREFACE
PREFACE:
PART ONE: THE BASICS
Where does layout design fit in the overall chip development process? Chapter 1
gives a nontechnical overview of the entire process so that we can understand the
layout designer’s role.
The mandate of an IC layout designer is to create the layout masks of
various portions of a chip in compliance with engineering drawings, netlist or
simulation results, and process design rules. To be capable of understanding
and respecting engineering drawings, the designer needs to understand basic
electricity rules and all the concepts related to the layout of gates. This will be
covered in Chapter 2.
Chapter 3 describes the manufacturing process and definition of layers. After
we understand how the layers are coordinated to generate devices and connectivity,
we learn about design rules. These are the manufacturing rules that must
be followed to ensure that the chip can be reliably manufactured. The process
engineers determine the minimum manufacturing grid, polygon, minimum distance
between layers, etc. The design rules are the rules that are the factor, which
together with the engineering drawings, netlist, etc., will fundamentally decide
the architecture of the chip.
PART TWO: LAYOUT STYLES
If a Layout Designer does not respect design requirements, the chip won’t work.
If the design rules are not respected, then the chip may not make it out of the prototyping
phase. The art of a good layout designer is to combine both, while taking
into consideration all the other aspects of a normal project: time to finish, final
size, quality, and so on. . . .
None of the chips just mentioned can claim that they are made up of only
one type of design style these days, so in Chapter 5 we talk about specialization
in design. We discuss full custom, standard cells, gate arrays, and other types of
techniques used in today’s ICs and the advantages and disadvantage of each type.
We talk about various techniques and methodologies used in complicated chips
for specific applications. The list is long, but some of them are clock generators,
datapath or register files, I/O cells, and memory types. We end the chapter with
chip finishing techniques.
PART THREE: ADVANCED TOPICS
The topic of Chapter 6 is related to the requirements of big chips for adequate connectivity
and power routing. We learn about methodologies to address all these
and discuss placement impact to routing, floorplanning techniques and results,
preplanned signals, etc.
Chapter 7 assumes that we know the basics and we start dealing with analog
problems, such as capacitors, electromigration, and 45-degree layout, to mention
Special process requirements are explained in Chapter 8. Learning about slits
in wide metals, step coverage, latch-up, and special design rules is possible now
that we understand even the most complicated process rules.
When the environment is uncertain, meaning that the process is not defined
yet or the design not 100 percent simulated, the layout designer has to face new
challenges. That’s why, in Chapter 9, we learn about contacts as cells, test pads,
spare logic gates and spare lines, and laying out a circuit with changes in mind.
PART FOUR: TOOLS OF THE TRADE
Perhaps the most exciting chapter is Chapter 10. This chapter analyzes various
EDA layout design tools required to face the challenges of any kind of layout
design. From crude polygon generation to place-and-route, from generators and
silicon compilers to verification tools, from plotting devices and software to transfer
formats, we try to show you a path through this maze of names, concepts,
methodologies, and usage. This chapter does not try to rate or recommend specific
tools, but it does try to enlighten the novice user about the choices in the marketplace
and how these tools might be adapted to different methodologies, and
vice versa.
This book is intended to help you protect yourself in a downpour of complicated
design methodologies pitched by EDA vendors, a world in which the
names of companies and tools change all the time, the hot topic each year is different,
and every year pundits at the Design Automation Conference are announcing
new catastrophes and solutions.
For example, first the machine was too small (CALMA). Then UNIX came
along and more memory was needed. Place-and-route appeared, along with
verification tools, extraction tools, and new terms like Deep Sub-Micron (DSM),
and so on. Even if the tools are solving most of today’s problems the market
requirements (prices) are always generating new “unsolved mysteries.”
This book is meant to help you prepare to understand the basic and
advanced concepts, and to learn how to analyze new methodologies and to understand
the philosophy of new tools. I hope that it will be useful for all of you, and
I will be more than happy to receive your comments. Please write me at the
following address:
Dan Clein
826 Riddell Avenue North
Ottawa, Ontario
Canada
K2A 2V9
cometic@ieee.org
only a few. |
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2006-11-27 08:27:30
