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A 3-A CMOS low-dropout regulator with adaptive Miller compensation
Abstract A 3-A CMOS low-dropout regulator (LDO) is
presented by utilizing adaptive Miller compensation (AMC)
technique, which provides high stability, as well as fast
line and load transient responses. The proposed LDO has
been fabricated in a standard 0.5 μm CMOS technology,
and the die area is small as 1330 μm×1330 μm with the
area-efficient waffle layout for power transistors. Both load
and line regulation are less than ±0.1%. And the output
voltage can recover within 80 μs for full load changes.
The power–supply rejection ratio (PSRR) at 20 KHz is
−30 dB.Moreover, it is stable enough with a ceramic capacitor
small to 2.2 μF, and the added series resistance is not
needed.
Keywords Adaptive Miller compensation . Loop-gain
stability . Low-dropout regulator . Waffle power transistors |
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