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Sigma Delta ADC for RF front end in 90nm__非常好论文
In this report a transistor-level design of a GHz sigma-delta analog-to-digital converter for
an RF front end is proposed. The design is current driven, where the integration
is done directly over two capacitances and it contains no operational amplifiers.
The clock frequency used for verification was 2.5 GHZ and the output bandwidth
was 10 MHz. The system is flexible in that the number of internal bits can
be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB
as well as a four-bit system yielding an SNR of 82.5 dB are analyzed. |
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