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FOUNDRY PROCESS QUALIFICATION GUIDELINES
(Wafer Fabrication Manufacturing Sites)
Contents
Page
Foreword ii
Introduction ii
Acronyms ii
1 Scope 1
2 Quality system 1
3 Responsibilities 1
3.1 Level 1 qualification 1
3.2 Level 2 qualification 2
4 Sample size 2
5 Use of packages 2
6 Reference documents 3
6.1 Industry standard documents 3
6.2 Selected references 5
7 Qualification test summary table 6
8 Interconnect reliability 7
8.1 Electromigration 7
8.2 Stress migration 9
8.3 Thermal cycling (copper interconnect) 11
8.4 Inter/intra-metal dielectric integrity 12
9 Conducting channel hot carrier injection (HCI) 13
9.1 DC conducting channel hot channel carrier (HCI) 13
10 Gate oxide integrity (GOI) 16
10.1 Voltage ramp dielectric breakdown (V-RAMP) & charge to breakdown (QBD) 16
10.2 Time-dependent dielectric breakdown (TDDB) 18
10.3 Plasma process-induced damage (P2ID) 21
11 Threshold voltage stability 23
11.1 Ionic contamination – bias temperature stress 23
11.2 Ionic contamination – triangular voltage sweep 24
11.3 Negative bias temperature instability in PMOS devices (NBTI) 25
12 Technology qualification vehicle (TQV) tests 26
12.1 Long term life test 26
12.2 Early life test 29
12.3 Temperature cycling test 32
12.4 Temperature-humidity-bias (THB) / highly accelerated stress test (HAST) 33
12.5 Yield data and defect density calculation 34
12.6 ESD characterization 35
12.7 Latch-up characterization 36
13 Process control monitor (PCM) characterization 37
13.1 PCM data 37
14 Construction analysis 40
14.1 Construction analysis 40
Annex A Differences between revisions 41 |
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