[内推] 成都 Synaptics inc. Senior DFT Engineer

chasing

location:

成都市天府软件园天府路A区8幢6楼

Salary:

1.5-3W

Job Tasks

• Be responsible for defining/Implementing different schemes of DFT aspects: including regular scan, at speed scan insertion, MBIST insertion, Boundary scan insertion, and functional test pattern generation.
• Be responsible for DFT verification both in RTL and netlist level.
• Be responsible for DFT related STA sign-off; work with Backend to drive full chip P&R and timing closure in DFT mode.
• Generate ATE test pattern, support test engineer to do ATE program development, support test engineer to do real silicon test on ATE.
  

Qualifications

Must Have

• MSEE/MSCS degree or equivalent
• Minimum 3 years’experience in DFT design field
• Strong knowledge of DFT including scan, ATPG, JTAG, BIST and analog IP test
• Independent full chip DFT task sign-off experience
• Experienced in ATE real silicon test
• Strong communications skill and capability
• Strong debug and problem-solving capability
  

• Self-motivated and good team player
  

Nice to have

• Strong Programming in Perl/TCL
• Experienced in DFT verification on emulator
• logic design and verification background with experience in STA
  

内推邮件：Kevin.Liu@synaptics.com