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本帖最后由 aeonsemi 于 2019-1-4 14:31 编辑
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创始人有多次创业成功经验，之前在Silicon Labs, Broadcom, ADI 担任副总，总经理等。团队有麻省理工，伯克利，斯坦福等多名博士硕士，沃顿商学院MBA等在业界有多年丰富经验的专业人士，并有国际一流的风投投资。如成功应聘硅谷职位，公司负责申请签证和申请绿卡。如成功应聘南京职位，公司负责到硅谷3个月培训。 ************************** Digital Frontend Designer ************************** Job Responsibilities:
• Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
Job Requirements:
• MS degree of EE with 3 years of work experience
• Familiar with verilog RTL design and Cadence design flow
• Familiar with unix/linux and scripts (Perl, Python, tcletc.)
• Communication English for talking and writing documents.
• Experience with UVM verification flow is preferred • Experience with Ethernet Packet Parser/Classification design preferred
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发表于 2019-1-4 09:36:15
